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Patent Agency Ranking
公开(公告)号：US09696830B2
公开(公告)日：2017-07-04
申请号：US14467546
申请日：2014-08-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jin-Han Kim , Yeong-Seop Lee , Seok-Hong Jeong , Myung-Sop Lee , Kyoung-Suk Oh , Jung-Hun Woo , Dong-Chul Lee , Jong-Hyun Yim , Sung-Il Jang , Yong-Gu Cho , Hyoung-Jun Go , Kyoung-Hun Kim , Jeong-Eun Kim , Hyeon-Beom Kim , Dae-Bin Noh , Jae-Young Park , Eun-Jin Baek , Chung-Hee Lee , Sung-Ho Jung , Jae-Wook Cho
CPC classification number: G06F3/041 , G06F1/1603 , G06F3/044 , G06F2203/04103 , Y10T29/49105
Abstract: Provided is a method of manufacturing a transparent circuit substrate for a touch screen. The method may involve forming an electrode layer on a transparent substrate, stacking a light shielding layer on the transparent substrate such that the light shielding layer is located on an outside of the electrode layer, stacking a mask on the light shielding layer and the electrode layer, forming a conductive layer on the mask, forming connecting lines for connecting the electrode layer and connecting terminals by removing the mask and a portion of the conductive layer, and forming the connecting terminals on the light shielding layer such that the connecting terminals contact the connecting lines.
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公开(公告)号：US20160093237A1
公开(公告)日：2016-03-31
申请号：US14851265
申请日：2015-09-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： HaJun LEE , Jin-Han Kim , Junho Song , SeongJong Yoo , Yeonwoo Jung , Yong-Hun Kim , Keemoon Chun
IPC: G09G3/20
CPC classification number: G09G3/3688 , G09G2310/0286 , G09G2310/0291 , G09G2310/0297 , G09G2310/08
Abstract: A source driver circuit is provided which includes a plurality of digital multi-spread (hereinafter referred to as “DMS”) blocks configured to generate DMS signals for controlling an output timing of a data signal to be transmitted to a display panel from a plurality of clocks which are delayed as much as a reference period one another. Each DMS block includes a plurality of sub blocks. Each of the sub blocks includes an enable signal generator and a delay unit. The enable signal generator generates an enable signal for outputting target DMS signals of the DMS signals using clocks selected from the plurality of clocks. The delay unit delays the DMS signals such that the DMS signals are sequentially delayed by the reference period.
Abstract translation: 提供了一种源驱动器电路，其包括多个数字多扩展（以下称为“DMS”）块，其被配置为生成DMS信号，用于控制要从多个数据传输到显示面板的数据信号的输出定时 时钟被延迟到另一个参考周期。 每个DMS块包括多个子块。 每个子块包括使能信号发生器和延迟单元。 使能信号发生器产生使能信号，用于使用从多个时钟中选择的时钟输出DMS信号的目标DMS信号。 延迟单元延迟DMS信号，使得DMS信号被顺序地延迟参考周期。
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公开(公告)号：US09275595B2
公开(公告)日：2016-03-01
申请号：US14185445
申请日：2014-02-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jin-Han Kim , Jae-Wook Kwon , Seong-Jong Yoo , Ha-Jun Lee
IPC: G09G3/26 , G09G3/36 , H03K5/04 , H03K19/003
CPC classification number: G09G3/3685 , G09G3/3688 , G09G2310/027 , G09G2310/0291 , H03K5/04 , H03K19/00361
Abstract: A source driving circuit includes an output buffer circuit to compensate for slew rate of signals used to drive a display device. The output buffer circuit includes a bias current control signal generating circuit and a channel amplifying circuit. The bias current control signal generating circuit performs an exclusive OR operation on an input signal and an output signal of a reference operational amplifier to generate a bias current control signal. The channel amplifying circuit adjusts the slew rate of a plurality of output voltage signals in response to the bias current control signal. The output signals are then used to control the display device.
Abstract translation: 源极驱动电路包括用于补偿用于驱动显示器件的信号的转换速率的输出缓冲器电路。 输出缓冲电路包括偏置电流控制信号发生电路和信道放大电路。 偏置电流控制信号发生电路对参考运算放大器的输入信号和输出信号执行异或运算，以产生偏置电流控制信号。 通道放大电路根据偏置电流控制信号调整多个输出电压信号的转换速率。 然后输出信号用于控制显示设备。
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4.发明授权公开(公告)号：US09928799B2
公开(公告)日：2018-03-27
申请号：US14851265
申请日：2015-09-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： HaJun Lee , Jin-Han Kim , Junho Song , SeongJong Yoo , Yeonwoo Jung , Yong-Hun Kim , Keemoon Chun
IPC: G09G3/36
CPC classification number: G09G3/3688 , G09G2310/0286 , G09G2310/0291 , G09G2310/0297 , G09G2310/08
Abstract: A source driver circuit is provided which includes a plurality of digital multi-spread (hereinafter referred to as “DMS”) blocks configured to generate DMS signals for controlling an output timing of a data signal to be transmitted to a display panel from a plurality of clocks which are delayed as much as a reference period one another. Each DMS block includes a plurality of sub blocks. Each of the sub blocks includes an enable signal generator and a delay unit. The enable signal generator generates an enable signal for outputting target DMS signals of the DMS signals using clocks selected from the plurality of clocks. The delay unit delays the DMS signals such that the DMS signals are sequentially delayed by the reference period.
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公开(公告)号：US09941785B2
公开(公告)日：2018-04-10
申请号：US14981314
申请日：2015-12-28
Inventor： Jin-Han Kim , Han Sol Seo , Bo Hyung Cho , Paul Jang , Sang Woo Kang
CPC classification number: H02M1/4225 , H02M1/44 , H02M2001/123 , Y02B70/126
Abstract: A power factor correction circuit and an electronic product including the same are disclosed. This technology configures a bridgeless circuit with no rectifier diode by using an additional switch, eliminating conduction loss due to the diode and reducing common mode EMI noise of the power factor correction circuit. A power factor correction circuit includes at least one inductor directly connected to an AC input stage, an output capacitor to smooth the output voltage, first switching elements to control current to store magnetic energy in the inductor, and a second switching element to maintain a substantially constant voltage between a ground voltage of an AC input stage and a ground voltage of an output stage.
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