公开(公告)号：US20160013160A1

公开(公告)日：2016-01-14

申请号：US14796506

申请日：2015-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-ho CHUN ,  Pil-kyu Kang ,  Byung-Iyul Park ,  Jae-hwa Park ,  Ju-il Choi

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L24/08 ,  H01L23/3192 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L24/05 ,  H01L24/80 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/08145 ,  H01L2224/80862 ,  H01L2224/80895 ,  H01L2224/80905 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2924/06 ,  H01L2924/0695 ,  H01L2924/07025 ,  H01L2224/80 ,  H01L2924/00014

Abstract: A wafer-to-wafer bonding structure may include: a first wafer including a first insulating layer on a first substrate and on a first copper (Cu) pad that penetrates the first insulating layer and has portions protruding from an upper surface of the first insulating layer, and a first barrier metal layer on a lower surface and sides of the first Cu pad; a second wafer including a second insulating layer on a second substrate and on a second copper (Cu) pad that penetrates the second insulating layer, has portions protruding from an upper surface of the second insulating layer, and is bonded to the first Cu pad, and a second barrier metal layer on a lower surface and sides of the second Cu pad; and a polymer layer covering protruding sides of the first and second barrier metal layers and disposed between the first and second wafers.

Abstract translation: 晶片到晶片接合结构可以包括：第一晶片，其包括在第一基板上的第一绝缘层和穿过第一绝缘层的第一铜（Cu）焊盘，并且具有从第一绝缘层的上表面突出的部分 层和第一Cu衬垫的下表面和侧面上的第一阻挡金属层; 包括在第二基板上的第二绝缘层和穿过第二绝缘层的第二铜（Cu）焊盘上的第二晶片具有从第二绝缘层的上表面突出的部分并且接合到第一Cu焊盘， 以及在所述第二Cu垫的下表面和侧面上的第二阻挡金属层; 以及覆盖第一和第二阻挡金属层的突出侧并设置在第一和第二晶片之间的聚合物层。

公开(公告)号：US20220108962A1

公开(公告)日：2022-04-07

申请号：US17551548

申请日：2021-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-gi JIN ,  Nae-in LEE ,  Jum-yong PARK ,  Jin-ho CHUN ,  Seong-min SON ,  Ho-Jin LEE

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.