公开(公告)号：US20240170291A1

公开(公告)日：2024-05-23

申请号：US17755298

申请日：2021-12-01

Applicant: HAESUNG DS CO., LTD.

Inventor： Jong Hoe Ku ,  In Seob Bae ,  Kwang Jae Yoo

IPC: H01L21/304 ,  H01L21/3213 ,  H01L23/00

CPC classification number: H01L21/3043 ,  H01L21/32134 ,  H01L24/29 ,  H01L24/45 ,  H01L2224/29021 ,  H01L2224/2919 ,  H01L2224/45005 ,  H01L2224/4502 ,  H01L2924/06

Abstract: A method of manufacturing a pre-mold substrate includes preparing an electrically conductive substrate, forming a groove on one surface of the substrate, arranging a resin to cover one surface of the substrate and the groove, removing a portion of the resin so that at least a portion of one surface of the substrate protrudes higher than a surface of the resin covering the groove, and forming a circuit pattern on another surface of the substrate.

公开(公告)号：US20180247906A1

公开(公告)日：2018-08-30

申请号：US15966447

申请日：2018-04-30

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Tieh-Chiang Wu

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05012 ,  H01L2224/05015 ,  H01L2224/05017 ,  H01L2224/05082 ,  H01L2224/051 ,  H01L2224/05111 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05551 ,  H01L2224/05558 ,  H01L2224/05578 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05686 ,  H01L2224/10125 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13018 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05341 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2924/01074

Abstract: A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.

公开(公告)号：US10056308B2

公开(公告)日：2018-08-21

申请号：US15431296

申请日：2017-02-13

Applicant: Intel Corporation

Inventor： Paul J. Gwin

IPC: H01L23/12 ,  H01L23/053 ,  H01L23/04 ,  H01L23/06 ,  G06F1/18 ,  H01L21/48 ,  H01L21/50 ,  H01L21/56 ,  H01L23/08 ,  H01L23/31 ,  H01L23/00 ,  H01L23/10

CPC classification number: H01L23/053 ,  G06F1/18 ,  H01L21/4803 ,  H01L21/481 ,  H01L21/4817 ,  H01L21/50 ,  H01L21/565 ,  H01L23/04 ,  H01L23/06 ,  H01L23/08 ,  H01L23/10 ,  H01L23/3142 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/0133 ,  H01L2924/06 ,  H01L2924/0615 ,  H01L2924/0635 ,  H01L2924/065 ,  H01L2924/068 ,  H01L2924/069 ,  H01L2924/0695 ,  H01L2924/0705 ,  H01L2924/10253 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/15153 ,  H01L2924/16152 ,  H01L2924/16176 ,  H01L2924/1619 ,  H01L2924/19105 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed toward a molded composite enclosure for an integrated circuit (IC) assembly. In one embodiment, an enclosure for an integrated circuit (IC) assembly may include a molded lid structure having a body portion, and a side portion that extends from the body portion and forms a cavity configured to house the IC assembly, wherein the body portion and the side portion share a contiguous interior material comprising a polymer and share a contiguous exterior material comprising a metal, the contiguous interior material having an opening formed in the body portion such that the IC assembly can be thermally coupled with the contiguous exterior material through the opening. Other embodiments may be described and/or claimed.

公开(公告)号：US10037955B2

公开(公告)日：2018-07-31

申请号：US15490716

申请日：2017-04-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/09 ,  H01L21/56 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49838 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/0214 ,  H01L2224/02175 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02315 ,  H01L2224/02331 ,  H01L2224/02335 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0381 ,  H01L2224/0382 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/06131 ,  H01L2224/06136 ,  H01L2224/06179 ,  H01L2224/0912 ,  H01L2224/11013 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/01051 ,  H01L2924/01047 ,  H01L2924/00012

Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to a second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element comprises a first side and a second side coupled to the first side. The first side and the second side of the transition element are non-tangential to the PPI pad.

公开(公告)号：US10020279B2

公开(公告)日：2018-07-10

申请号：US15209269

申请日：2016-07-13

Applicant: International Business Machines Corporation

Inventor： Wei Lin ,  Leathen Shi ,  Spyridon Skordas ,  Kevin R. Winstel

IPC: H01L23/00 ,  H01L33/00 ,  H01L21/18

CPC classification number: H01L24/32 ,  H01L21/187 ,  H01L21/76251 ,  H01L21/76254 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/80 ,  H01L24/83 ,  H01L24/94 ,  H01L33/0079 ,  H01L2224/03452 ,  H01L2224/03845 ,  H01L2224/04 ,  H01L2224/04026 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05187 ,  H01L2224/0519 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/08145 ,  H01L2224/27452 ,  H01L2224/27616 ,  H01L2224/29023 ,  H01L2224/29083 ,  H01L2224/29187 ,  H01L2224/32145 ,  H01L2224/80896 ,  H01L2224/80907 ,  H01L2224/80948 ,  H01L2224/81896 ,  H01L2224/83 ,  H01L2224/838 ,  H01L2224/83896 ,  H01L2224/83907 ,  H01L2224/83948 ,  H01L2224/94 ,  H01L2924/05442 ,  H01L2924/06 ,  H01L2924/0715 ,  H01L2924/3512 ,  H01L2924/35121 ,  Y02P80/30 ,  H01L2224/80 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.

公开(公告)号：US09997486B2

公开(公告)日：2018-06-12

申请号：US15115827

申请日：2015-02-03

Applicant: DEXERIALS CORPORATION

Inventor： Yasushi Akutsu ,  Reiji Tsukao

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  B32B27/18 ,  C09J4/00 ,  C09J7/00 ,  C09J9/02 ,  C09J163/00 ,  C09J201/00 ,  H01B1/02 ,  C08F220/18 ,  B32B27/08 ,  B32B27/20 ,  B32B27/38 ,  B32B27/14 ,  H01R4/04 ,  H05K3/32

CPC classification number: H01L24/29 ,  B32B27/08 ,  B32B27/14 ,  B32B27/18 ,  B32B27/20 ,  B32B27/38 ,  B32B2307/202 ,  B32B2457/00 ,  C08F220/18 ,  C08K2201/001 ,  C09J4/00 ,  C09J7/00 ,  C09J7/10 ,  C09J9/02 ,  C09J163/00 ,  C09J201/00 ,  C09J2201/36 ,  C09J2201/602 ,  C09J2203/326 ,  C09J2205/102 ,  C09J2433/00 ,  C09J2463/00 ,  H01B1/02 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/16225 ,  H01L2224/27003 ,  H01L2224/271 ,  H01L2224/27848 ,  H01L2224/29082 ,  H01L2224/29083 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29357 ,  H01L2224/29364 ,  H01L2224/2939 ,  H01L2224/294 ,  H01L2224/29499 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81903 ,  H01L2224/83101 ,  H01L2224/83204 ,  H01L2224/83851 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/83907 ,  H01L2924/06 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/2021 ,  H01L2924/2064 ,  H01L2924/3511 ,  H01R4/04 ,  H05K3/323 ,  H01L2924/00014 ,  H01L2924/07811 ,  H01L2924/066 ,  H01L2924/0675 ,  H01L2924/069 ,  H01L2924/07025 ,  H01L2924/061 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An anisotropic conductive film has a first connection layer and a second connection layer formed on surface of the first connection layer. The first connection layer is a photopolymerized resin layer, and the second connection layer is a thermo- or photo-cationically, anionically, or radically polymerizable resin layer. On the surface of first connection layer on the side of second connection layer, conductive particles for anisotropic conductive connection are arranged in a single layer. A region in which the curing ratio is lower than that of the surface of the first connection layer exists in a direction oblique to the thickness direction of the first connection layer. Alternatively, the curing ratio of a region relatively near another surface of the first connection layer among regions of the first connection layer in the vicinity of the conductive particles is lower than that of the surface of the first connection layer.

公开(公告)号：US20180150667A1

公开(公告)日：2018-05-31

申请号：US15877978

申请日：2018-01-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Yu-Feng Chen ,  Chih-Hua Chen ,  Hao-Yi Tsai ,  Chung-Shi Liu

IPC: G06K9/00 ,  H01L21/56 ,  H01L25/16 ,  H01L23/00 ,  H01L23/498 ,  H01L23/48 ,  H01L23/31 ,  H01L21/768

CPC classification number: G06K9/0002 ,  G06K9/0004 ,  H01L21/56 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/17 ,  H01L24/81 ,  H01L25/16 ,  H01L2224/0231 ,  H01L2224/02372 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/8101 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/15311 ,  H01L2924/2064

Abstract: A fingerprint sensor package and method are provided. The fingerprint sensor package comprises a fingerprint sensor along with a fingerprint sensor surface material and electrical connections from a first side of the fingerprint sensor to a second side of the fingerprint sensor. A high voltage chip is connected to the fingerprint sensor and then the fingerprint sensor package with the high voltage chip are connected to a substrate, wherein the substrate has an opening to accommodate the presence of the high voltage chip.

公开(公告)号：US09859257B2

公开(公告)日：2018-01-02

申请号：US15358380

申请日：2016-11-22

Applicant: Invensas Corporation

Inventor： Javier A. Delacruz ,  Belgacem Haba ,  Tu Tam Vu ,  Rajesh Katkar

IPC: H01L23/495 ,  H01L21/00 ,  H01L25/065 ,  H01L25/10 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49555 ,  H01L23/49575 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/49051 ,  H01L2224/4909 ,  H01L2224/49113 ,  H01L2224/49173 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/06 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: Stacked microelectronic packages comprise microelectronic elements each having a contact-bearing front surface and edge surfaces extending away therefrom, and a dielectric encapsulation region contacting an edge surface. The encapsulation defines first and second major surfaces of the package and a remote surface between the major surfaces. Package contacts at the remote surface include a first set of contacts at positions closer to the first major surface than a second set of contacts, which instead are at positions closer to the second major surface. The packages are configured such that major surfaces of each package can be oriented in a nonparallel direction with the major surface of a substrate, the package contacts electrically coupled to corresponding contacts at the substrate surface. The package stacking and orientation can provide increased packing density.

公开(公告)号：US20170345713A1

公开(公告)日：2017-11-30

申请号：US15638551

申请日：2017-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-ho Chun ,  Byung-lyul PARK ,  Hyun-soo CHUNG ,  Gil-heyun CHOI ,  Son-kwan HWANG

IPC: H01L21/768 ,  H01L23/00 ,  H01L25/065 ,  H01L23/48 ,  H01L23/544 ,  H01L23/31

CPC classification number: H01L21/76898 ,  H01L21/768 ,  H01L21/76841 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/544 ,  H01L24/03 ,  H01L24/81 ,  H01L25/065 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05025 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13023 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8185 ,  H01L2924/00014 ,  H01L2924/06 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00

Abstract: A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer.

公开(公告)号：US09748190B2

公开(公告)日：2017-08-29

申请号：US14604294

申请日：2015-01-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Yu Chen ,  Lin-Chih Huang ,  Tsang-Jiuh Wu ,  Tasi-Jung Wu ,  Wen-Chih Chiou

IPC: H01L23/00 ,  H01L21/683 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065

CPC classification number: H01L24/14 ,  H01L21/6835 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/96 ,  H01L25/0657 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/11424 ,  H01L2224/11464 ,  H01L2224/13025 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/96 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2224/81

Abstract: Methods of making and an integrated circuit device. An embodiment method includes patterning a first polymer layer disposed over a first copper seed layer, electroplating a through polymer via in the first polymer layer using the first copper seed layer, a via end surface offset from a first polymer layer surface, forming a second polymer layer over the first polymer layer, the second polymer layer patterned to expose the via end surface, and electroplating an interconnect in the second polymer layer to cap the via end surface using a second copper seed layer.