公开(公告)号：US20160013160A1

公开(公告)日：2016-01-14

申请号：US14796506

申请日：2015-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-ho CHUN ,  Pil-kyu Kang ,  Byung-Iyul Park ,  Jae-hwa Park ,  Ju-il Choi

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L24/08 ,  H01L23/3192 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L24/05 ,  H01L24/80 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/08145 ,  H01L2224/80862 ,  H01L2224/80895 ,  H01L2224/80905 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2924/06 ,  H01L2924/0695 ,  H01L2924/07025 ,  H01L2224/80 ,  H01L2924/00014

Abstract: A wafer-to-wafer bonding structure may include: a first wafer including a first insulating layer on a first substrate and on a first copper (Cu) pad that penetrates the first insulating layer and has portions protruding from an upper surface of the first insulating layer, and a first barrier metal layer on a lower surface and sides of the first Cu pad; a second wafer including a second insulating layer on a second substrate and on a second copper (Cu) pad that penetrates the second insulating layer, has portions protruding from an upper surface of the second insulating layer, and is bonded to the first Cu pad, and a second barrier metal layer on a lower surface and sides of the second Cu pad; and a polymer layer covering protruding sides of the first and second barrier metal layers and disposed between the first and second wafers.

Abstract translation: 晶片到晶片接合结构可以包括：第一晶片，其包括在第一基板上的第一绝缘层和穿过第一绝缘层的第一铜（Cu）焊盘，并且具有从第一绝缘层的上表面突出的部分 层和第一Cu衬垫的下表面和侧面上的第一阻挡金属层; 包括在第二基板上的第二绝缘层和穿过第二绝缘层的第二铜（Cu）焊盘上的第二晶片具有从第二绝缘层的上表面突出的部分并且接合到第一Cu焊盘， 以及在所述第二Cu垫的下表面和侧面上的第二阻挡金属层; 以及覆盖第一和第二阻挡金属层的突出侧并设置在第一和第二晶片之间的聚合物层。

公开(公告)号：US10153219B2

公开(公告)日：2018-12-11

申请号：US15629072

申请日：2017-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyung-jun Jeon ,  Nae-in Lee ,  Byung-Iyul Park

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/045 ,  H01L23/047 ,  H01L25/10 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package of a package on package type includes a lower package including a printed circuit board (PCB) substrate including a plurality of base layers and a cavity penetrating the plurality of base layers, a first semiconductor chip in the cavity. a redistribution structure on a first surface of the PCB substrate and on an active surface of the first semiconductor chip, a first cover layer covering the redistribution structure, and the second cover layer covering a second surface of the PCB substrate and an inactive surface of the first semiconductor chip, and an upper package on the second cover layer of the lower package and including a second semiconductor chip.

公开(公告)号：US09698051B2

公开(公告)日：2017-07-04

申请号：US14590036

申请日：2015-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-ho Chun ,  Byung-Iyul Park ,  Hyun-soo Chung ,  Gil-heyun Choi ,  Son-kwan Hwang

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/24 ,  H01L21/768 ,  H01L25/065 ,  H01L23/544 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/76898 ,  H01L21/768 ,  H01L21/76841 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/544 ,  H01L24/03 ,  H01L24/81 ,  H01L25/065 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05025 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13023 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8185 ,  H01L2924/00014 ,  H01L2924/06 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00

Abstract: A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer.

公开(公告)号：US20130221519A1

公开(公告)日：2013-08-29

申请号：US13753774

申请日：2013-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Son-kwan Hwang ,  Byung-Iyul Park ,  Hyun-soo Chung ,  Jin-ho Chun ,  Gil-heyun Choi

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L23/3107 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/16225 ,  H01L2224/17517 ,  H01L2924/15311

Abstract: A semiconductor device includes a substrate on which integrated circuit units are formed, main solder bumps that are electrically connected to the integrated circuit units on the substrate and dummy solder bumps that are not electrically connected to the integrated circuit units on the substrate. The dummy solder bumps are narrower than wiring patterns immediately below the dummy solder bumps.

Abstract translation: 半导体器件包括其上形成有集成电路单元的基板，与基板上的集成电路单元电连接的主要焊料凸块和未电连接到基板上的集成电路单元的虚拟焊料凸块。 虚拟焊料凸块比虚拟焊料凸块正下方的布线图形窄。