公开(公告)号：US20190013206A1

公开(公告)日：2019-01-10

申请号：US15844681

申请日：2017-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hoon PARK ,  Joong Shik SHIN ,  BYOUNG IL LEE ,  Jong Ho WOO ,  Eun Taek JUNG ,  Jun Ho CHA

IPC: H01L21/3105 ,  H01L27/11531 ,  H01L21/763 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/11573 ,  H01L27/11592

Abstract: A semiconductor device includes a substrate having a first region and a second region, the first region including memory cells, and the second region including transistors for driving the memory cells, and device isolation regions disposed within the substrate to define active regions of the substrate. The active regions include a first guard active region surrounding the first region, a second guard active region surrounding a portion of the second region, and at least one dummy active region disposed between the first guard active region and the second guard active region.

公开(公告)号：US20240081079A1

公开(公告)日：2024-03-07

申请号：US18341201

申请日：2023-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Ji NOH ,  Jong Ho WOO ,  Min Jun LEE

IPC: H10B51/20 ,  H01L23/522 ,  H01L23/528 ,  H01L29/78 ,  H10B51/10

CPC classification number: H10B51/20 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/78391 ,  H10B51/10

Abstract: Provided is a semiconductor device. The semiconductor device includes a substrate; a first interlayer insulating layer, on the substrate, comprising a first interconnection; a common source plate on the first interlayer insulating layer; a conductive layer extending in a first direction on the common source plate; a ferroelectric layer on one sidewall of the conductive layer; a channel layer on the ferroelectric layer; a first conductive pillar, on the channel layer, penetrating the common source plate and being connected to the first interconnection; and a second conductive pillar, on the channel layer, spaced apart from the first conductive pillar in the first direction and connected to the common source plate, the ferroelectric layer and the channel layer between the common source plate and the first conductive pillar.

公开(公告)号：US20240015977A1

公开(公告)日：2024-01-11

申请号：US18217730

申请日：2023-07-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Jun LEE ,  Jong Ho WOO ,  Yong Seok KIM

IPC: H10B51/20 ,  H10B51/10 ,  H10B51/30 ,  G11C11/22 ,  G11C5/06 ,  H01L29/78

CPC classification number: H10B51/20 ,  H10B51/10 ,  H10B51/30 ,  G11C11/223 ,  G11C5/063 ,  H01L29/78391 ,  G11C11/2275 ,  G11C11/2273 ,  H01L29/6684

Abstract: A non-volatile memory device includes a substrate; an insulating layer on the substrate; a bit line isolation layer on the insulating layer; a common source line conductive layer on the bit line isolation layer; a ferroelectric memory cell on the bit line isolation layer; a bit line connected to a top of the ferroelectric memory cell; and a common source line connected to the common source line conductive layer and electrically connected to the ferroelectric memory cell, wherein the ferroelectric memory cell includes a ferroelectric layer, a channel layer, a first conductive filler connected to the ferroelectric layer and the channel layer and extending in a vertical direction, and a second conductive filler connected to the ferroelectric layer and the channel layer and extending in the vertical direction, the first conductive filler is connected to the bit line, and the second conductive filler is connected to the common source line.