公开(公告)号：US20240081079A1

公开(公告)日：2024-03-07

申请号：US18341201

申请日：2023-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Ji NOH ,  Jong Ho WOO ,  Min Jun LEE

IPC: H10B51/20 ,  H01L23/522 ,  H01L23/528 ,  H01L29/78 ,  H10B51/10

CPC classification number: H10B51/20 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/78391 ,  H10B51/10

Abstract: Provided is a semiconductor device. The semiconductor device includes a substrate; a first interlayer insulating layer, on the substrate, comprising a first interconnection; a common source plate on the first interlayer insulating layer; a conductive layer extending in a first direction on the common source plate; a ferroelectric layer on one sidewall of the conductive layer; a channel layer on the ferroelectric layer; a first conductive pillar, on the channel layer, penetrating the common source plate and being connected to the first interconnection; and a second conductive pillar, on the channel layer, spaced apart from the first conductive pillar in the first direction and connected to the common source plate, the ferroelectric layer and the channel layer between the common source plate and the first conductive pillar.

公开(公告)号：US20240015977A1

公开(公告)日：2024-01-11

申请号：US18217730

申请日：2023-07-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Jun LEE ,  Jong Ho WOO ,  Yong Seok KIM

IPC: H10B51/20 ,  H10B51/10 ,  H10B51/30 ,  G11C11/22 ,  G11C5/06 ,  H01L29/78

CPC classification number: H10B51/20 ,  H10B51/10 ,  H10B51/30 ,  G11C11/223 ,  G11C5/063 ,  H01L29/78391 ,  G11C11/2275 ,  G11C11/2273 ,  H01L29/6684

Abstract: A non-volatile memory device includes a substrate; an insulating layer on the substrate; a bit line isolation layer on the insulating layer; a common source line conductive layer on the bit line isolation layer; a ferroelectric memory cell on the bit line isolation layer; a bit line connected to a top of the ferroelectric memory cell; and a common source line connected to the common source line conductive layer and electrically connected to the ferroelectric memory cell, wherein the ferroelectric memory cell includes a ferroelectric layer, a channel layer, a first conductive filler connected to the ferroelectric layer and the channel layer and extending in a vertical direction, and a second conductive filler connected to the ferroelectric layer and the channel layer and extending in the vertical direction, the first conductive filler is connected to the bit line, and the second conductive filler is connected to the common source line.

公开(公告)号：US20240258430A1

公开(公告)日：2024-08-01

申请号：US18383065

申请日：2023-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Il PARK ,  Min Jun LEE ,  Jae Hyun PARK

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66795

Abstract: Disclosed is a semiconductor device including a first channel layer on a substrate, and a second channel layer on the first channel layer, the first and second channel layers extending in a first direction while being spaced apart from the substrate, and including a 2D semiconductor material, a gate structure on the substrate, the gate structure extending in a second direction, and being penetrated by the first and second channel layers, and source/drain contacts on side surfaces of the gate structure and being connected to the first and second channel layers. The gate structure includes a first gate portion between the substrate and the first channel layer and having a first gate length, a second gate portion between the first and second channel layers and having a second gate length, and a third gate portion on an upper surface of the second channel layer and having a third gate length.

公开(公告)号：US20230397443A1

公开(公告)日：2023-12-07

申请号：US18111921

申请日：2023-02-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Jun LEE ,  Yong Seok KIM

IPC: H10B63/00 ,  G11C13/00

CPC classification number: H10B63/845 ,  H10B63/34 ,  G11C13/0004 ,  G11C13/004 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/79

Abstract: A resistive memory device includes: a substrate; a plurality of row lines extending in a first direction and spaced apart from each other in a second direction and a third direction, on the substrate, wherein the first direction, the second direction, and the third direction intersect each other; a plurality of column lines extending in the second direction and spaced apart from each other in the first direction, on the substrate; a plurality of upper selection lines extending in the second direction, between the row lines and the column lines; a channel layer extending in the third direction and connected to the plurality of row lines; and a first impurity region and a second impurity region spaced apart from each other in the third direction with the upper selection line interposed therebetween.