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    SEMICONDUCTOR PACKAGE
    1.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20240379622A1

    公开(公告)日：2024-11-14

    申请号：US18531140

    申请日：2023-12-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sung Yun WOO ,  Ji Min Choi ,  Joong Won Shin ,  Yeon Jin Lee ,  Jong Min Lee

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

    Abstract: A semiconductor package includes a base chip including a top surface extending in a first horizontal direction and a second horizontal direction intersecting the first horizontal direction, a semiconductor chip stack including a first semiconductor chip and a second semiconductor chip which are sequentially stacked on the base chip in a vertical direction and are aligned on respective sides in the vertical direction, first through vias penetrating the base chip and spaced apart from each other in the first horizontal direction, second through vias penetrating the first semiconductor chip and spaced apart from each other in the first horizontal direction, third through vias penetrating the second semiconductor chip and spaced apart from each other in the first horizontal direction, first connection pads contacting the first through vias, second connection pads contacting the second through vias, and third connection pads contacting the third through vias.

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220271044A1

    公开(公告)日：2022-08-25

    申请号：US17515888

    申请日：2021-11-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seok Hyun Kim ,  Young Sin Kim ,  Dong Sik Park ,  Jong Min Lee ,  Joon Yong Choe

    IPC: H01L27/108 ,  H01L29/66 ,  H01L21/768

    Abstract: A semiconductor device comprises a substrate comprising a cell region; a cell region isolation film in the substrate and extending along an outer edge of the cell region; a bit-line structure on the substrate and in the cell region, wherein the bit-line structure has a distal end positioned on the cell region isolation film; a cell spacer on a vertical side surface of the distal end of the bit-line structure; an etching stopper film extending along a side surface of the cell spacer and a top face of the cell region isolation film; and an interlayer insulating film on the etching stopper film, and on the side surface of the cell spacer, wherein the interlayer insulating film includes silicon nitride.

    Method of preparing furfural compounds
    6.
    发明授权
    Method of preparing furfural compounds 有权
    糠醛化合物的制备方法

    公开(公告)号：US09469619B2

    公开(公告)日：2016-10-18

    申请号：US14066541

    申请日：2013-10-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong Min Lee ,  Hyeon Su Heo ,  Moo Ho Lee ,  Kyung Hae Lee

    IPC: C07D307/46 ,  C07D307/48 ,  C07D307/50

    CPC classification number: C07D307/46 ,  C07D307/48 ,  C07D307/50

    Abstract: Provided is a two-step method of producing a compound of chemical formula 1 in the presence of an alcohol solvent and a Group 3B metal catalyst or a salt thereof, comprising a first step comprising alkylation or isomerization of an aldohexose-containing substrate to obtain an intermediate, and a second step comprising dehydration of the intermediate to produce a compound of chemical formula 1. Preferably, additional solvent and/or catalyst are not added in the second step.

    Abstract translation: 本发明提供了在醇溶剂和3B族金属催化剂或其盐的存在下制备化学式1的化合物的两步法，该方法包括第一步骤，包括含醛糖基底物的烷基化或异构化以获得 中间体和第二步，包括中间体的脱水以产生化学式1的化合物。优选在第二步中不加入另外的溶剂和/或催化剂。

    Memory module and memory system comprising same
    7.
    发明授权
    Memory module and memory system comprising same 有权
    内存模块和包含它的存储器系统

    公开(公告)号：US09099166B2

    公开(公告)日：2015-08-04

    申请号：US14157070

    申请日：2014-01-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jun Hee Shin ,  Won Hyung Song ,  Jong Min Lee ,  You Keun Han

    IPC: G11C8/06 ,  G11C5/04 ,  G11C7/10

    CPC classification number: G11C8/06 ,  G11C5/04 ,  G11C7/1045

    Abstract: A memory module comprises a plurality of semiconductor memory devices each comprising a mode register set (MRS) circuit configured to generate an enable signal corresponding to an error mode of the semiconductor memory device in response to an MRS command received from a command decoder, and an address buffer configured to store a predetermined address signal, to receive an address signal and corresponding data from an external device, and to compare the address signal received with the predetermined address signal in response to the enable signal. As a consequence of determining that the address signal received from the external device is the same as the predetermined address signal stored in the address buffer, data different from the corresponding data received from the external device is written to a memory cell corresponding to the predetermined address signal.

    Abstract translation: 存储器模块包括多个半导体存储器件，每个半导体存储器件包括模式寄存器集（MRS）电路，其被配置为响应于从命令解码器接收到的MRS命令产生对应于半导体存储器件的错误模式的使能信号，以及 地址缓冲器，其被配置为存储预定的地址信号，以从外部设备接收地址信号和对应的数据，并且响应于所述使能信号来比较与所述预定地址信号接收的地址信号。 作为确定从外部设备接收的地址信号与存储在地址缓冲器中的预定地址信号相同的结果，与从外部设备接收到的对应数据不同的数据被写入到与预定地址对应的存储单元 信号。

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