公开(公告)号：US20240413206A1

公开(公告)日：2024-12-12

申请号：US18409559

申请日：2024-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Jun Nam ,  Jin Bum Kim ,  Sang Moon Lee ,  Gyeom Kim ,  Hyo Jin Kim ,  Tae Hyung Lee ,  In Geon Hwang

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device includes: a substrate, an active pattern extending in a first horizontal direction on the substrate, a plurality of nanosheets spaced apart from each other and stacked in a vertical direction on the active pattern, a gate electrode extending in a second horizontal direction different from the first horizontal direction on the active pattern, the gate electrode surrounding the plurality of nanosheets, a source/drain region disposed on at least one side of the gate electrode on the active pattern, the source/drain region including a first layer doped with a metal, and a second layer disposed on the first layer, and an inner spacer disposed between the gate electrode and the first layer, between each of the plurality of nanosheets, the inner spacer in contact with the first layer, the inner spacer including a metal oxide formed by oxidizing the same material as the metal.

公开(公告)号：US20230411529A1

公开(公告)日：2023-12-21

申请号：US18160297

申请日：2023-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo Jin Kim ,  Sang Moon Lee ,  Jin Bum Kim ,  Yong Jun Nam

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8234

CPC classification number: H01L29/78672 ,  H01L29/78696 ,  H01L29/0673 ,  H01L29/0847 ,  H01L21/823412 ,  H01L21/823418

Abstract: A semiconductor device includes a lower pattern extending in a first direction, a first blocking structure which is on the lower pattern and includes at least one first blocking film comprising an oxygen-doped crystalline silicon film, a source/drain pattern on the first blocking structure, and a gate structure which extends in a second direction on the lower pattern and includes a gate electrode and a gate insulating film. Related fabrication methods are also discussed.

公开(公告)号：US20220399330A1

公开(公告)日：2022-12-15

申请号：US17571954

申请日：2022-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung In Choi ,  Do Young Choi ,  Dong Myoung Kim ,  Jin Bum Kim ,  Hae Jun Yu

IPC: H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a semiconductor substrate having first and second regions therein, a first lower semiconductor pattern, which protrudes from the semiconductor substrate in the first region and extends in a first direction across the semiconductor substrate, and a first gate electrode, which extends across the first lower semiconductor pattern and the semiconductor substrate in a second direction. A plurality of semiconductor sheet patterns are provided, which are spaced apart from each other in a third direction to thereby define a vertical stack of semiconductor sheet patterns, on the first lower semiconductor pattern. A first gate insulating film is provided, which separates the plurality of semiconductor sheet patterns from the first gate electrode. A second lower semiconductor pattern is provided, which protrudes from the semiconductor substrate in the second region. A plurality of wire patterns are provided, which are spaced apart from each other on the second lower semiconductor pattern. A second gate insulating film is wrapped around each of the plurality of wire patterns.

公开(公告)号：US20240014304A1

公开(公告)日：2024-01-11

申请号：US18170104

申请日：2023-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Bin Chun ,  Jin Bum Kim ,  Dong Suk Shin ,  Gyeom Kim ,  Da Hye Kim

IPC: H01L29/775 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08

CPC classification number: H01L29/775 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/42392 ,  H01L29/0847

Abstract: A semiconductor device includes a lower pattern on a substrate and protruding in a first direction, a source/drain pattern on the lower pattern and including a semiconductor liner film in contact with the lower pattern, and an epitaxial insulating liner extending along at least a portion of a sidewall of the semiconductor liner film, wherein the epitaxial insulating liner is in contact with the semiconductor liner film, wherein the semiconductor liner film includes a first portion, wherein the first portion of the semiconductor liner film includes a first point spaced apart from the lower pattern at a first height, and a second point spaced apart from the lower pattern at a second height, wherein the second height is greater than the first height, wherein a width of the semiconductor liner film in a second direction at the first point is less than a width of the semiconductor liner film in the second direction at the second point, and wherein the epitaxial insulating liner extends along at least a portion of a sidewall of the first portion of the semiconductor liner film.

公开(公告)号：US20230420519A1

公开(公告)日：2023-12-28

申请号：US18110950

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Da Hye Kim ,  Gyeom Kim ,  Jin Bum Kim ,  Su Jin Jung ,  Kyung Bin Chun

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/161 ,  H01L29/423 ,  H01L29/775 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/02532 ,  H01L29/66545 ,  H01L29/66439

Abstract: A semiconductor device having improved performance and reliability. The semiconductor device may include a lower pattern extending in a first direction, and a plurality of sheet patterns spaced apart from the lower pattern in a second direction perpendicular to the first direction. A plurality of gate structures may be on the lower pattern and spaced apart in the first direction, and a source/drain pattern, which may include a semiconductor liner film and a semiconductor filling film on the semiconductor liner film. A liner recess that is defined by an inner surface of the semiconductor liner film may include a plurality of width extension regions, and a width of each width extension region in the first direction may increase and then decreases, as a distance increases in the second direction from an upper surface of the lower pattern.

公开(公告)号：US10128112B2

公开(公告)日：2018-11-13

申请号：US15595945

申请日：2017-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cho Eun Lee ,  Jin Bum Kim ,  Kang Hun Moon ,  Jae Myung Choe ,  Sun Jung Kim ,  Dong Suk Shin ,  Il Gyou Shin ,  Jeong Ho Yoo

IPC: H01L21/336 ,  H01L21/02 ,  H01L21/223 ,  H01L29/66

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a dummy gate electrode on a substrate, forming a trench on a side surface of the dummy gate electrode, performing a bake process of removing an impurity from the trench and forming a source/drain in the trench, wherein the bake process comprises a first stage and a second stage following the first stage, an air pressure in which the substrate is disposed during the first stage is different from an air pressure in which the substrate is disposed during the second stage, and the bake process is performed while the substrate is on a stage rotating the substrate, wherein a revolution per minute (RPM) of the substrate during the first stage is different from a revolution per minute (RPM) of the substrate during the second stage.

公开(公告)号：US09899497B2

公开(公告)日：2018-02-20

申请号：US15355781

申请日：2016-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Bum Kim ,  Kang Hun Moon ,  Choeun Lee ,  Kyung Yub Jeon ,  Sujin Jung ,  Haegeon Jung ,  Yang Xu

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming an active pattern protruding orthogonally from a substrate; forming a preliminary gate structure on the active pattern to cross the active pattern; etching the active pattern to form preliminary recess regions at both sides of the preliminary gate structure, wherein each of the preliminary recess regions is formed to define a delta region in an upper portion of the active pattern; forming a sacrificial layer on inner side surfaces and a bottom surface of the active pattern exposed by each of the preliminary recess regions; etching the delta regions and the sacrificial layer to form recess regions having a ‘U’-shaped section; and forming source/drain regions in the recess regions.

公开(公告)号：US09859387B2

公开(公告)日：2018-01-02

申请号：US14990793

申请日：2016-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Bum Kim ,  Chul Sung Kim ,  Kang Hun Moon ,  Yang Xu ,  Bon Young Koo

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/36 ,  H01L29/45 ,  H01L29/66 ,  H01L27/11 ,  H01L29/775 ,  H01L29/06

CPC classification number: H01L29/41791 ,  H01L27/1104 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/36 ,  H01L29/41758 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: A semiconductor device includes a substrate having an upper surface, a plurality of active fins on the substrate, a gate electrode crossing the plurality of active fins, and at each side of the gate electrode, a source/drain region on the plurality of active fins. The source/drain region may include a plurality of first regions extending from the active fins, and a second region between each of the plurality of first regions. The second region may have a second germanium concentration greater than the first germanium concentration. The source/drain region may be connected to a contact plug, and may have a top surface that has a wave shaped, or curved surface. The top surface may have a larger surface area than a top surface of the contact plug.

公开(公告)号：US20240363712A1

公开(公告)日：2024-10-31

申请号：US18505279

申请日：2023-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Moon Lee ,  Jin Bum Kim ,  Hyo Jin Kim ,  Yong Jun Nam ,  In Geon Hwang

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823807 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device may include a substrate, an active pattern extended in a first horizontal direction on the substrate, a plurality of nanosheets stacked and spaced apart from each other in a vertical direction on the active pattern, a gate electrode extended in a second horizontal direction different from the first horizontal direction on the active pattern, the gate electrode surrounding the plurality of nanosheets, a source/drain region on both sides of the plurality of nanosheets in the first horizontal direction on the active pattern, a gate insulating layer between the plurality of nanosheets and the gate electrode, and a doping layer between the plurality of nanosheets and the gate insulating layer, the doping layer including silicon (Si) or silicon germanium (SiGe) and doped with a doping material, at least a portion of the doping layer overlapping an uppermost nanosheet of the plurality of nanosheets in the first horizontal direction.

公开(公告)号：US11735663B2

公开(公告)日：2023-08-22

申请号：US17565650

申请日：2021-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Bum Kim ,  Gyeom Kim ,  Da Hye Kim ,  Jae Mun Kim ,  Il Gyou Shin ,  Seung Hun Lee ,  Kyung In Choi

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7849 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: Example semiconductor devices and methods for fabricating a semiconductor device are disclosed. An example device may include a substrate, a first semiconductor pattern spaced apart from the substrate, a first antioxidant pattern extending along a bottom surface of the first semiconductor pattern and spaced apart from the substrate, and a field insulating film on the substrate. The insulating film may cover at least a part of a side wall of the first semiconductor pattern. The first antioxidant pattern may include a first semiconductor material film doped with a first impurity.