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    Semiconductor devices and methods of manufacturing the same
    2.
    发明授权
    Semiconductor devices and methods of manufacturing the same 有权

    公开(公告)号：US10910261B2

    公开(公告)日：2021-02-02

    申请号：US16577429

    申请日：2019-09-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byoungdeog Choi ,  JungWoo Seo ,  Sangyeon Han ,  Hyun-Woo Chung ,  Hongrae Kim ,  Yoosang Hwang

    IPC: H01L27/108 ,  H01L21/768 ,  H01L23/498 ,  H01L27/22 ,  H01L27/24 ,  H01L45/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

    Abstract: A semiconductor device includes bit line structures on a substrate, the bit line structures extending along a first direction and being spaced apart from each other along a second direction perpendicular to the first direction, contact plugs spaced apart from each other along the first direction and being on active regions of the substrate between adjacent bit line structures, a linear spacer on each longitudinal sidewall of a bit line structure, landing pads on the contact plugs, respectively, the landing pads being electrically connected to the contact plugs, respectively, and landing pads that are adjacent to each other along the first direction being offset with respect to each other along the second direction, as viewed in a top view, a conductive pad between each of the contact plugs and a corresponding active region, a vertical axes of the conductive pad and corresponding active region being horizontally offset.

    Semiconductor memory device
    3.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11289488B2

    公开(公告)日：2022-03-29

    申请号：US16744572

    申请日：2020-01-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joongchan Shin ,  Jiyoung Kim ,  Hui-Jung Kim ,  Taehyun An ,  Eunju Cho ,  Hyungeun Choi ,  Sangyeon Han

    IPC: H01L27/108 ,  G11C5/06

    Abstract: Disclosed is a semiconductor memory device including a stack structure including layers which are vertically stacked on a substrate and each of which includes a bit line extending in a first direction and a semiconductor pattern extending in a second direction from the bit line, a gate electrode which is in a hole penetrating the stack structure and extending along a stack of semiconductor patterns, a vertical insulating layer covering the gate electrode and filling the hole, and a data storage element electrically connected to the semiconductor pattern. The data storage element includes a first electrode, which is in a first recess of the vertical insulating layer and has a cylindrical shape whose one end is opened, and a second electrode, which includes a first protrusion in a cylinder of the first electrode and a second protrusion in a second recess of the vertical insulating layer.

    SEMICONDUCTOR DEVICES HAVING BURIED GATES
    4.
    发明申请
    SEMICONDUCTOR DEVICES HAVING BURIED GATES 有权

    公开(公告)号：US20220077154A1

    公开(公告)日：2022-03-10

    申请号：US17318563

    申请日：2021-05-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Huijung Kim ,  Minwoo Kwon ,  Sangyeon Han ,  Sangwon Kim ,  Junsoo Kim ,  Hyeonjin Shin ,  Eunkyu Lee

    IPC: H01L27/108 ,  H01L29/78 ,  H01L29/423

    Abstract: A semiconductor device includes a substrate including an active region, a gate structure disposed in a gate trench in the substrate, a bit line disposed on the substrate and electrically connected to the active region on one side of the gate structure, and a capacitor disposed on the bit line and electrically connected to the active region on another side of the gate structure. The gate structure includes a gate dielectric layer disposed on bottom and inner side surfaces of the gate trench, a conductive layer disposed on the gate dielectric layer in a lower portion of the gate trench, sidewall insulating layers disposed on the gate dielectric layer, on an upper surface of the conductive layer, a graphene conductive layer disposed on the conductive layer, and a buried insulating layer disposed between the sidewall insulating layers on the graphene conductive layer.

    SEMICONDUCTOR DEVICES HAVING BURIED GATES
    7.
    发明公开
    SEMICONDUCTOR DEVICES HAVING BURIED GATES 审中-公开

    公开(公告)号：US20230247824A1

    公开(公告)日：2023-08-03

    申请号：US18298230

    申请日：2023-04-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： HUIJUNG KIM ,  Minwoo Kwon ,  Sangyeon Han ,  Sangwon Kim ,  Junsoo Kim ,  Hyeonjin Shin ,  Eunkyu Lee

    IPC: H01L29/94 ,  H01L29/423 ,  H01L29/78

    CPC classification number: H10B12/34 ,  H10B12/315 ,  H10B12/053 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/7813

    Abstract: A semiconductor device includes a substrate including an active region, a gate structure disposed in a gate trench in the substrate, a bit line disposed on the substrate and electrically connected to the active region on one side of the gate structure, and a capacitor disposed on the bit line and electrically connected to the active region on another side of the gate structure. The gate structure includes a gate dielectric layer disposed on bottom and inner side surfaces of the gate trench, a conductive layer disposed on the gate dielectric layer in a lower portion of the gate trench, sidewall insulating layers disposed on the gate dielectric layer, on an upper surface of the conductive layer, a graphene conductive layer disposed on the conductive layer, and a buried insulating layer disposed between the sidewall insulating layers on the graphene conductive layer.

    Semiconductor memory device and method of fabricating the same
    10.
    发明授权
    Semiconductor memory device and method of fabricating the same 有权

    公开(公告)号：US11114440B2

    公开(公告)日：2021-09-07

    申请号：US16805066

    申请日：2020-02-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jungwoo Song ,  Kwangmin Kim ,  Jun Ho Lee ,  Hyuckjin Kang ,  Yong Kwan Kim ,  Sangyeon Han ,  Seguen Park

    IPC: H01L21/768 ,  H01L27/108 ,  H01L29/06 ,  H01L23/532 ,  H01L27/24 ,  H01L27/22

    Abstract: Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.

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