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公开(公告)号：US20220068859A1
公开(公告)日：2022-03-03
申请号：US17207242
申请日：2021-03-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyungeun Choi , Eun-Ji Kim , Jong-Ho Moon , Hyoungyol Mun , Han-Sik Yoo , Kiseok Lee , Seungjae Jung , Taehyun An , Sangyeon Han , Yoosang Hwang
IPC: H01L23/00 , H01L27/108 , G11C11/408 , G11C11/4091 , H01L25/065 , H01L25/18
Abstract: A three-dimensional semiconductor memory device is provided. The device may include a first substrate including a bit-line connection region and a word-line connection region, a cell array structure on the first substrate, a second substrate including a first core region and a second core region, which are respectively overlapped with the bit-line connection region and the word-line connection region, and a peripheral circuit structure on the second substrate.
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公开(公告)号：US10340022B2
公开(公告)日：2019-07-02
申请号：US15977553
申请日：2018-05-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Eun-Ji Kim , Jung-June Park , Jeong-Don Ihm , Byung-Hoon Jeong , Young-Don Choi
Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.
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3.发明授权公开(公告)号：US09559002B2
公开(公告)日：2017-01-31
申请号：US14804831
申请日：2015-07-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seung-Taek Lee , Eun-Ji Kim , Sin-Woo Kang , Yeong-Lyeol Park , Sung-Dong Cho
IPC: H01L21/768 , H01L21/308 , H01L21/3105 , H01L21/762 , H01L23/48 , H01L25/065 , H01L23/522 , H01L21/8234 , H01L23/532
CPC classification number: H01L21/76898 , H01L21/3083 , H01L21/31053 , H01L21/762 , H01L21/76229 , H01L21/76807 , H01L21/76834 , H01L21/823475 , H01L21/823481 , H01L23/481 , H01L23/5226 , H01L23/53238 , H01L24/05 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L2224/05559 , H01L2224/0557 , H01L2224/05571 , H01L2224/06181 , H01L2224/10126 , H01L2224/13025 , H01L2224/131 , H01L2224/13147 , H01L2224/16146 , H01L2224/17181 , H01L2224/73204 , H01L2924/00012 , H01L2924/00014 , H01L2924/014
Abstract: A semiconductor device includes a circuit device on a substrate and a first insulating interlayer on the substrate and covering the circuit device. An electrode structure extends through the first insulating interlayer and at least partially through the substrate. An etch-stop layer pattern is disposed on a sidewall of the electrode structure on a side of the first insulating layer opposite the substrate. A blocking layer pattern is disposed on the etch-stop layer pattern. The device further includes an interconnection structure including a via portion passing through the blocking layer pattern to contact the through electrode structure and a wiring portion on the via portion and having a different width than the via portion. The semiconductor device may further include a contact plug electrically connected to the circuit device through the first insulating interlayer. The contact plug and the through electrode structure may include different metals.
Abstract translation: 半导体器件包括衬底上的电路器件和衬底上的第一绝缘中间层并覆盖电路器件。 电极结构延伸穿过第一绝缘中间层并且至少部分地穿过衬底。 蚀刻停止层图案设置在与基板相对的第一绝缘层一侧的电极结构的侧壁上。 阻挡层图案设置在蚀刻停止层图案上。 该装置还包括互连结构，其包括穿过阻挡层图案的通孔部分，以与通孔电极结构接触，并且在通孔部分上具有与通孔部分不同的宽度的布线部分。 半导体器件还可以包括通过第一绝缘中间层电连接到电路器件的接触插塞。 接触插塞和通孔电极结构可以包括不同的金属。
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公开(公告)号：US11705166B2
公开(公告)日：2023-07-18
申请号：US17182357
申请日：2021-02-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Eun-Ji Kim , Jung-June Park , Jeong-Don Ihm , Byung-Hoon Jeong , Young-Don Choi
IPC: G11C7/10
CPC classification number: G11C7/1048 , G11C7/1057 , G11C7/1084 , G11C2207/105
Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.
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公开(公告)号：US10742369B2
公开(公告)日：2020-08-11
申请号：US15807240
申请日：2017-11-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seong-Jun Song , Kyung-Hwan Jo , Eun-Ji Kim , Jae-Hyun Kwon , Sungjin Kim , Donginn Seo , Dohyeon Lee , Seung Chul Lee
Abstract: An electronic device is provided. The electronic device includes a first antenna for a first band and a second band, a second antenna for the second band and a third band and a pre-processing unit configured to generate, based on identifying a frequency band of a first signal received via the first antenna and a frequency band of a second signal received via the second antenna are the second band, a pre-processed signal by combining the first signal and the second signal based on a ratio of a weight factor, and to transmit the pre-processed signal to a first radio frequency (RF) receiver.
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Patent Agency Ranking
公开(公告)号：US10672436B2
公开(公告)日：2020-06-02
申请号：US16058709
申请日：2018-08-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Eun-Ji Kim , Jung-June Park , Jeong-Don Ihm , Byung-Hoon Jeong , Young-Don Choi
IPC: G11C7/10
Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.
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公开(公告)号：US10559373B2
公开(公告)日：2020-02-11
申请号：US16458933
申请日：2019-07-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Eun-Ji Kim , Jung-June Park , Jeong-Don Ihm , Byung-Hoon Jeong , Young-Don Choi
Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.
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8.发明申请公开(公告)号：US20160020145A1
公开(公告)日：2016-01-21
申请号：US14804831
申请日：2015-07-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seung-Taek Lee , Eun-Ji Kim , Sin-Woo Kang , Yeong-Lyeol Park , Sung-Dong Cho
IPC: H01L21/768 , H01L21/8234 , H01L21/3105 , H01L21/762 , H01L21/308 , H01L23/532
CPC classification number: H01L21/76898 , H01L21/3083 , H01L21/31053 , H01L21/762 , H01L21/76229 , H01L21/76807 , H01L21/76834 , H01L21/823475 , H01L21/823481 , H01L23/481 , H01L23/5226 , H01L23/53238 , H01L24/05 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L2224/05559 , H01L2224/0557 , H01L2224/05571 , H01L2224/06181 , H01L2224/10126 , H01L2224/13025 , H01L2224/131 , H01L2224/13147 , H01L2224/16146 , H01L2224/17181 , H01L2224/73204 , H01L2924/00012 , H01L2924/00014 , H01L2924/014
Abstract: A semiconductor device includes a circuit device on a substrate and a first insulating interlayer on the substrate and covering the circuit device. An electrode structure extends through the first insulating interlayer and at least partially through the substrate. An etch-stop layer pattern is disposed on a sidewall of the electrode structure on a side of the first insulating layer opposite the substrate. A blocking layer pattern is disposed on the etch-stop layer pattern. The device further includes an interconnection structure including a via portion passing through the blocking layer pattern to contact the through electrode structure and a wiring portion on the via portion and having a different width than the via portion. The semiconductor device may further include a contact plug electrically connected to the circuit device through the first insulating interlayer. The contact plug and the through electrode structure may include different metals.
Abstract translation: 半导体器件包括衬底上的电路器件和衬底上的第一绝缘中间层并覆盖电路器件。 电极结构延伸穿过第一绝缘中间层并且至少部分地穿过衬底。 蚀刻停止层图案设置在与基板相对的第一绝缘层一侧的电极结构的侧壁上。 阻挡层图案设置在蚀刻停止层图案上。 该装置还包括互连结构，其包括穿过阻挡层图案的通孔部分，以与通孔电极结构接触，并且在通孔部分上具有与通孔部分不同的宽度的布线部分。 半导体器件还可以包括通过第一绝缘中间层电连接到电路器件的接触插塞。 接触插塞和通孔电极结构可以包括不同的金属。
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公开(公告)号：US11024400B2
公开(公告)日：2021-06-01
申请号：US16862624
申请日：2020-04-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Eun-Ji Kim , Jung-June Park , Jeong-Don Ihm , Byung-Hoon Jeong , Young-Don Choi
Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.
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公开(公告)号：US10964360B2
公开(公告)日：2021-03-30
申请号：US16875163
申请日：2020-05-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Eun-Ji Kim , Jung-June Park , Jeong-Don Ihm , Byung-Hoon Jeong , Young-Don Choi
IPC: G11C7/10
Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.
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