公开(公告)号：US09099166B2

公开(公告)日：2015-08-04

申请号：US14157070

申请日：2014-01-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Hee Shin ,  Won Hyung Song ,  Jong Min Lee ,  You Keun Han

IPC: G11C8/06 ,  G11C5/04 ,  G11C7/10

CPC classification number: G11C8/06 ,  G11C5/04 ,  G11C7/1045

Abstract: A memory module comprises a plurality of semiconductor memory devices each comprising a mode register set (MRS) circuit configured to generate an enable signal corresponding to an error mode of the semiconductor memory device in response to an MRS command received from a command decoder, and an address buffer configured to store a predetermined address signal, to receive an address signal and corresponding data from an external device, and to compare the address signal received with the predetermined address signal in response to the enable signal. As a consequence of determining that the address signal received from the external device is the same as the predetermined address signal stored in the address buffer, data different from the corresponding data received from the external device is written to a memory cell corresponding to the predetermined address signal.

Abstract translation: 存储器模块包括多个半导体存储器件，每个半导体存储器件包括模式寄存器集（MRS）电路，其被配置为响应于从命令解码器接收到的MRS命令产生对应于半导体存储器件的错误模式的使能信号，以及 地址缓冲器，其被配置为存储预定的地址信号，以从外部设备接收地址信号和对应的数据，并且响应于所述使能信号来比较与所述预定地址信号接收的地址信号。 作为确定从外部设备接收的地址信号与存储在地址缓冲器中的预定地址信号相同的结果，与从外部设备接收到的对应数据不同的数据被写入到与预定地址对应的存储单元 信号。

公开(公告)号：US09164139B2

公开(公告)日：2015-10-20

申请号：US13962233

申请日：2013-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Hee Shin ,  Young Man Ahn ,  Seung Mo Jung ,  You Keun Han ,  Sang Jhun Hwang

IPC: G01R31/02 ,  G01R31/01 ,  G01R31/26 ,  G11C11/4096 ,  G11C5/04 ,  G11C29/12 ,  G01R31/27 ,  G11C7/10 ,  G11C29/02 ,  G11C29/14 ,  G11C29/04 ,  G11C29/40 ,  G06F13/28 ,  G11C11/406 ,  H03M13/00 ,  H03M7/40 ,  G06F17/50

CPC classification number: G01R31/02 ,  G01R31/01 ,  G01R31/26 ,  G01R31/27 ,  G06F13/28 ,  G06F17/5054 ,  G11C5/04 ,  G11C7/1012 ,  G11C7/1021 ,  G11C7/1036 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/406 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/1201 ,  G11C29/14 ,  G11C2029/0401 ,  G11C2029/4002 ,  H03M7/40 ,  H03M13/00

Abstract: A memory device includes a memory cell array and a data input/output circuit. The memory cell array includes a plurality of memory cells connected to a plurality of bit lines and a plurality of word lines. The data input/output circuit is configured to receive data from external data pins of the memory device, output the received data to the memory cell array through a plurality of input/output lines electrically coupled to the plurality of bit lines, receive data read from the memory cell array through the plurality of input/output lines, and output the read data through the external data pins. For each external data pin, the data input/output circuit is configured to output data received at the external data pin to a corresponding input/output line. The corresponding input/output line is selected in response to bit values of a set of bits included in the received data.

Abstract translation: 存储器件包括存储单元阵列和数据输入/输出电路。 存储单元阵列包括连接到多个位线和多个字线的多个存储单元。 数据输入/输出电路被配置为从存储器件的外部数据引脚接收数据，通过电耦合到多个位线的多个输入/输出线将接收到的数据输出到存储单元阵列，从多个位线读取数据 通过多个输入/输出线的存储单元阵列，并通过外部数据引脚输出读取的数据。 对于每个外部数据引脚，数据输入/输出电路被配置为将在外部数据引脚处接收的数据输出到相应的输入/输出线。 响应于包含在接收数据中的一组位的位值来选择相应的输入/输出线。