公开(公告)号：US20210202516A1

公开(公告)日：2021-07-01

申请号：US16912894

申请日：2020-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kang Min KIM ,  Jin Hyuk KIM ,  Jung Tae SUNG ,  Joong Shik SHIN ,  Sung Hyung LEE

IPC: H01L27/11578 ,  G11C7/18 ,  H01L29/08 ,  H01L29/06

Abstract: A semiconductor device includes a first substrate including a cell region and surrounded by an extension region, a common source plate on the first substrate, a supporter on the common source plate, a first stack structure on the supporter and including an alternately stacked first insulating film and first gate electrode, a channel hole penetrating the first stack structure, the supporter, and the common source plate on the cell region, and an electrode isolation trench spaced apart from the channel hole in a first direction on the cell region, extending in a second direction, and penetrating the first stack structure, the supporter, and the common source plate, wherein a first thickness of the supporter in a first region adjacent to the electrode isolation trench is greater than a second thickness of the supporter in a second region formed between the electrode isolation trench and the channel hole.

公开(公告)号：US20230369212A1

公开(公告)日：2023-11-16

申请号：US18117623

申请日：2023-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Tae SUNG ,  Yun Sun Jang ,  Moo Rym Choi

IPC: H01L23/528 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

CPC classification number: H01L23/5283 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

Abstract: A nonvolatile memory device includes a plurality of metal lines extending in a first direction and stacked in a second direction crossing the first direction, a plurality of cell structures passing through the plurality of metal lines and extending in the second direction, a plurality of extension regions, a plate common source line contact connected with a common source line, extending in the first direction, and formed in least two of the plurality of extension regions that are not formed with the plurality of cell structures, and input/output metal contacts connected with an external connection pad, extending in the first direction, and formed with at least two of the plurality of extension regions that are not formed with the plate common source line contact.

公开(公告)号：US20230165007A1

公开(公告)日：2023-05-25

申请号：US17951337

申请日：2022-09-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun Sun JANG ,  Moo Rym CHOI ,  Jung Tae SUNG

IPC: H01L27/11573 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  G11C16/04

CPC classification number: H01L27/11573 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  G11C16/0483

Abstract: A semiconductor memory device has a peripheral logic structure including a peripheral logic substrate and a peripheral logic insulating film on the peripheral logic substrate. A cell array structure includes a cell substrate and a source structure that are sequentially stacked on the peripheral logic structure. A bypass via electrically connects the cell substrate and the peripheral logic substrate. The bypass via has a linear shape extending in at least one of first and second directions on the cell substrate. The first and second directions are parallel to an upper surface of the cell substrate.

公开(公告)号：US20210375906A1

公开(公告)日：2021-12-02

申请号：US17399239

申请日：2021-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kang Min KIM ,  Jin Hyuk KIM ,  Jung Tae SUNG ,  Joong Shik SHIN ,  Sung Hyung LEE

IPC: H01L27/11578 ,  H01L29/06 ,  H01L29/08 ,  G11C7/18

Abstract: A semiconductor device includes a first substrate including a cell region and surrounded by an extension region, a common source plate on the first substrate, a supporter on the common source plate, a first stack structure on the supporter and including an alternately stacked first insulating film and first gate electrode, a channel hole penetrating the first stack structure, the supporter, and the common source plate on the cell region, and an electrode isolation trench spaced apart from the channel hole in a first direction on the cell region, extending in a second direction, and penetrating the first stack structure, the supporter, and the common source plate, wherein a first thickness of the supporter in a first region adjacent to the electrode isolation trench is greater than a second thickness of the supporter in a second region formed between the electrode isolation trench and the channel hole.