公开(公告)号：US10509681B2

公开(公告)日：2019-12-17

申请号：US15812299

申请日：2017-11-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-hoon Kim ,  Ju-hyun Kim ,  Min-seok Kim

IPC: G06F9/46 ,  G06F9/50 ,  G06F9/48 ,  G06F9/52

Abstract: A resource management method of an electronic apparatus according to an example embodiment includes storing resource information including at least one resource category for assorting hardware resources and software resources by type and an attribute category indicating attribute information of resources included in the at least one resource category in a memory of the electronic apparatus, and in response to an application requesting a specific resource, allocating the specific resource to the application based on the resource information.

公开(公告)号：US20200185598A1

公开(公告)日：2020-06-11

申请号：US16512503

申请日：2019-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-sun Noh ,  Ju-hyun Kim ,  Joon-myoung Lee ,  Woo-chang Lim

IPC: H01L43/04 ,  H01L27/22 ,  H01L43/06 ,  H01L43/10 ,  H01L43/14 ,  G11C11/16 ,  H01F10/32 ,  H01F41/30 ,  G11C11/18

Abstract: A magnetic memory device includes a buffer layer on a substrate, a magnetic tunnel junction structure including a fixed layer structure, a tunnel barrier, and a free layer that are sequentially arranged on the buffer layer, and a spin-orbit torque (SOT) structure on the magnetic tunnel junction structure and including a topological insulator material, wherein the free layer includes a Heusler material.

公开(公告)号：US10249817B2

公开(公告)日：2019-04-02

申请号：US15678098

申请日：2017-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-woong Kim ,  Kee-won Kim ,  Se-chung Oh ,  Yong-sung Park ,  Ju-hyun Kim

IPC: H01L29/82 ,  H01L43/10 ,  H01L43/08 ,  H01L27/22

Abstract: A magnetic device includes a free layer; a pinned layer; a tunnel barrier disposed between the free layer and the pinned layer; a polarization enhancement layer disposed between the tunnel barrier and the pinned layer; and a blocking layer disposed between the polarization enhancement layer and the pinned layer, wherein the blocking layer includes a first diffusion trap layer and a second diffusion trap layer disposed on the first diffusion trap layer.

公开(公告)号：US10516388B1

公开(公告)日：2019-12-24

申请号：US16263210

申请日：2019-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye-jin Kim ,  Hyun-bae Kim ,  Ju-hyun Kim ,  Ji-hwan Kim ,  Chan-hee Park ,  Young-hwan Choi

IPC: G05F3/02 ,  H03K3/64 ,  H01J37/32 ,  G05F3/08 ,  H03K3/021

Abstract: A voltage generator includes a pulse circuit and a slope circuit. The pulse circuit is to apply voltages of three different levels to an output terminal and the slope circuit is to apply a slope voltage to the output terminal. The slope circuit includes an inductor to take current out of a capacitive load connected to the output terminal.

公开(公告)号：US10892400B2

公开(公告)日：2021-01-12

申请号：US16512503

申请日：2019-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-sun Noh ,  Ju-hyun Kim ,  Joon-myoung Lee ,  Woo-chang Lim

IPC: H01L43/04 ,  H01L27/22 ,  H01L43/06 ,  H01L43/10 ,  G11C11/16 ,  H01F10/32 ,  H01F41/30 ,  G11C11/18 ,  H01L43/14

Abstract: A magnetic memory device includes a buffer layer on a substrate, a magnetic tunnel junction structure including a fixed layer structure, a tunnel barrier, and a free layer that are sequentially arranged on the buffer layer, and a spin-orbit torque (SOT) structure on the magnetic tunnel junction structure and including a topological insulator material, wherein the free layer includes a Heusler material.

公开(公告)号：US10686122B2

公开(公告)日：2020-06-16

申请号：US15983255

申请日：2018-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-hwan Park ,  Ju-hyun Kim ,  Se-chung Oh ,  Dong-kyu Lee ,  Jung-min Lee ,  Kyung-il Hong

IPC: H01L43/02 ,  H01L43/12 ,  H01L23/532 ,  H01L27/22 ,  H01L23/538 ,  H01L45/00 ,  H01L27/24 ,  G11C11/16 ,  G11C13/00

Abstract: A variable resistance memory device includes a metal interconnection layer on a substrate, an interlayer insulating layer on the metal interconnection layer and defining a contact hole for exposing a portion of the metal interconnection layer, a barrier metal layer including a plurality of sub-barrier metal layers inside the contact hole, a plug metal layer on the barrier metal layer and burying the contact hole, and a variable resistance structure on the barrier metal layer and the plug metal layer.

公开(公告)号：US20200161198A1

公开(公告)日：2020-05-21

申请号：US16383815

申请日：2019-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung-jae Park ,  Ju-hyun Kim

IPC: H01L21/66 ,  H01L27/088 ,  H01L29/78

Abstract: A test pattern group includes a plurality of test patterns. Each of the plurality of test patterns includes a substrate including a first region and a second region, a first fin group and a second fin group each including fins extending on the first region of the substrate and the second region of the substrate. a first gate structure and a second gate structure each positioned on the first fin group and formed to intersect with the fins of the first fin group and the second fin group, a first source/drain contact formed on a first source/drain, a second source/drain contact formed on a second source/drain, a first gate contact formed on the first gate structure, and a second gate contact formed on the second gate structure. The number of fins included in the first fin group is greater than the number of fins included in the second fin group.