公开(公告)号：US10249817B2

公开(公告)日：2019-04-02

申请号：US15678098

申请日：2017-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-woong Kim ,  Kee-won Kim ,  Se-chung Oh ,  Yong-sung Park ,  Ju-hyun Kim

IPC: H01L29/82 ,  H01L43/10 ,  H01L43/08 ,  H01L27/22

Abstract: A magnetic device includes a free layer; a pinned layer; a tunnel barrier disposed between the free layer and the pinned layer; a polarization enhancement layer disposed between the tunnel barrier and the pinned layer; and a blocking layer disposed between the polarization enhancement layer and the pinned layer, wherein the blocking layer includes a first diffusion trap layer and a second diffusion trap layer disposed on the first diffusion trap layer.

公开(公告)号：US10686122B2

公开(公告)日：2020-06-16

申请号：US15983255

申请日：2018-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-hwan Park ,  Ju-hyun Kim ,  Se-chung Oh ,  Dong-kyu Lee ,  Jung-min Lee ,  Kyung-il Hong

IPC: H01L43/02 ,  H01L43/12 ,  H01L23/532 ,  H01L27/22 ,  H01L23/538 ,  H01L45/00 ,  H01L27/24 ,  G11C11/16 ,  G11C13/00

Abstract: A variable resistance memory device includes a metal interconnection layer on a substrate, an interlayer insulating layer on the metal interconnection layer and defining a contact hole for exposing a portion of the metal interconnection layer, a barrier metal layer including a plurality of sub-barrier metal layers inside the contact hole, a plug metal layer on the barrier metal layer and burying the contact hole, and a variable resistance structure on the barrier metal layer and the plug metal layer.

公开(公告)号：US20190123262A1

公开(公告)日：2019-04-25

申请号：US15993862

申请日：2018-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon-myoung Lee ,  Jae-hoon Kim ,  Yong-sung Park ,  Se-chung Oh ,  Jun-ho Jeong

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16

Abstract: Provided is a semiconductor manufacturing apparatus including a transfer chamber, a first process chamber connected to the transfer chamber, and a second process chamber connected to the transfer chamber. The transfer chamber may be configured to transfer a substrate. The first process chamber may be configured to perform a first oxidation process for oxidizing a metal layer on the substrate at a first temperature. The second process chamber may be configured to perform a second oxidation process for oxidizing a metal layer on the substrate at a second temperature higher than the first temperature.

公开(公告)号：US09985202B2

公开(公告)日：2018-05-29

申请号：US15365977

申请日：2016-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeong-heon Park ,  Se-chung Oh ,  Byoung-jae Bae ,  Jong-chul Park

IPC: H01L21/00 ,  H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A method of fabricating a memory device, the method including forming a first magnetization layer; forming a tunnel barrier layer on the first magnetization layer; forming a second magnetization layer on the tunnel barrier layer; forming a magnetic tunnel junction (MTJ) structure by patterning the first magnetization layer, the tunnel barrier layer, and the second magnetization layer; and forming a boron oxide in a sidewall of the MTJ structure by implanting boron.