公开(公告)号：US20200098708A1

公开(公告)日：2020-03-26

申请号：US16696917

申请日：2019-11-26

申请人： Samsung Electronics Co., Ltd.

发明人： Ki Cheol BAE ,  Chul Woo PARK ,  Kwang Sub LEE ,  Sang Gyun LEE ,  Se Young JANG ,  Chi Hyun CHO

IPC分类号： H01L23/64 ,  H01L49/02 ,  H01L25/18 ,  H01L25/10 ,  H01L25/16

摘要： A semiconductor assembly with a package on package (POP) structure includes a first semiconductor package having a first lower substrate, a first upper substrate facing the first lower substrate, and a first semiconductor chip mounted on an area of the first lower substrate. The POP structure further includes a second semiconductor package having a second lower substrate stacked on the first semiconductor package and spaced apart from the first semiconductor package, and a second semiconductor chip mounted in an area of the second lower substrate. At least one passive element is disposed in one of the first upper substrate and the second lower substrate and electrically connected to the second semiconductor chip.

公开(公告)号：US20170358544A1

公开(公告)日：2017-12-14

申请号：US15617973

申请日：2017-06-08

申请人： Samsung Electronics Co., Ltd.

发明人： Ki Cheol BAE ,  Chul Woo Park ,  Kwang Sub Lee ,  Sang Gyun Lee ,  Se Young Jang ,  Chi Hyun Cho

IPC分类号： H01L23/64 ,  H01L49/02 ,  H01L25/10 ,  H01L25/18

CPC分类号： H01L23/645 ,  H01L23/3128 ,  H01L23/642 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L28/40 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83851 ,  H01L2224/92247 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30101 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor assembly with a package on package (POP) structure includes a first semiconductor package having a first lower substrate, a first upper substrate facing the first lower substrate, and a first semiconductor chip mounted on an area of the first lower substrate. The POP structure further includes a second semiconductor package having a second lower substrate stacked on the first semiconductor package and spaced apart from the first semiconductor package, and a second semiconductor chip mounted in an area of the second lower substrate. At least one passive element is disposed in one of the first upper substrate and the second lower substrate and electrically connected to the second semiconductor chip.