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公开(公告)号：US11681579B2
公开(公告)日：2023-06-20
申请号：US17344180
申请日：2021-06-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dae-Hyun Kim , Yong-Gyu Chu , Jun Jin Kong , Ki-Jun Lee , Myung-Kyu Lee
IPC: G06F11/10 , G11C29/52 , G06F13/16 , G11C11/401 , H01L25/065 , G11C11/4096 , G11C29/42 , G06F21/55
CPC classification number: G06F11/1068 , G06F13/1668 , G11C11/401 , G11C29/52 , H01L25/0657 , G06F11/1012 , G06F11/1032 , G06F21/554 , G11C11/4096 , G11C29/42 , H01L2225/06513 , H01L2225/06541
Abstract: A semiconductor memory device includes: a memory cell array including a plurality of memory cells; an error correction code (ECC) engine configured to detect and/or correct at least one error bit in read data and configured to generate a decoding status flag indicative of whether the at least one error bit is detected and/or corrected, wherein the read data is read from the memory cell array; a channel interface circuit configured to receive the read data and the decoding status flag from the ECC engine and configured to transmit the read data and the decoding status flag to a memory controller, wherein the channel interface circuit is configured to transmit the decoding status flag to the memory controller through a pin; and a control logic circuit configured to control the ECC engine and the channel interface circuit in response to an address and a command from the memory controller.
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Patent Agency Ranking
公开(公告)号：US11036578B2
公开(公告)日：2021-06-15
申请号：US16217249
申请日：2018-12-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dae-Hyun Kim , Yong-Gyu Chu , Jun Jin Kong , Ki-Jun Lee , Myung-Kyu Lee
IPC: G06F11/10 , G11C29/52 , G06F13/16 , G11C11/401 , H01L25/065 , G11C11/4096 , G11C29/42 , G06F21/55
Abstract: A semiconductor memory device includes: a memory cell array including a plurality of memory cells; an error correction code (ECC) engine configured to detect and/or correct at least one error bit in read data and configured to generate a decoding status flag indicative of whether the at least one error bit is detected and/or corrected, wherein the read data is read from the memory cell array; a channel interface circuit configured to receive the read data and the decoding status flag from the ECC engine and configured to transmit the read data and the decoding status flag to a memory controller, wherein the channel interface circuit is configured to transmit the decoding status flag to the memory controller through a pin; and a control logic circuit configured to control the ECC engine and the channel interface circuit in response to an address and a command from the memory controller.
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公开(公告)号：US10922171B2
公开(公告)日：2021-02-16
申请号：US16441287
申请日：2019-06-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-Hye Cho , Ki-Jun Lee , Myung-Kyu Lee , Jun Jin Kong
Abstract: An error correction code (ECC) circuit of a semiconductor memory device includes a syndrome generation circuit and a correction circuit. The syndrome generation circuit generates syndrome based on a message and first parity bits in a codeword read from a memory cell array by using one of a first parity check matrix and a second parity check matrix, in response to a decoding mode signal. The correction circuit receives the codeword, corrects at least a portion of (t1+t2) error bits in the codeword based on the syndrome and outputs a corrected message. Here, t1 and t2 are natural numbers, respectively.
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公开(公告)号：US10942805B2
公开(公告)日：2021-03-09
申请号：US16444056
申请日：2019-06-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Young-Jun Hwang , Myung-Kyu Lee , Hong-Rak Son , Geun-Yeong Yu , Ki-Jun Lee
Abstract: An error correcting circuit receives a codeword including user data and a parity code, and performs an error correction operation on the user data. The circuit includes a first buffer, a decoder, a second buffer and a processor. The first buffer stores the codeword and sequentially outputs pieces of subgroup data obtained by dividing the codeword. The decoder generates pieces of integrity data for each of the pieces of subgroup data received from the first buffer, and performs the error correction operation on the user data using the parity code. The second buffer sequentially stores the pieces of integrity data for each of the pieces of subgroup data. The processor determines whether an error is present in the codeword based on the pieces of integrity data stored in the second buffer when at least one of the pieces of integrity data is updated in the second buffer.
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公开(公告)号：US09819361B2
公开(公告)日：2017-11-14
申请号：US14645073
申请日：2015-03-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dong-Min Shin , Jun-jin Kong , Ki-Jun Lee , Myung-Kyu Lee , Kyeong-Cheol Yang , Seung-Chan Lim
CPC classification number: H03M13/13 , H03M13/134
Abstract: A list decoding method for a polar code includes generating a tree-type decoding graph for input codeword symbols; the generating a tree-type decoding graph including, generating a decoding path list to which a decoding edge is added based on a reliability of a decoding path, the decoding path list being generated such that, among decoding paths generated based on the decoding edge, decoding paths within a threshold number of critical paths survive within the decoding path list in an order of high likelihood probability, and determining an estimation value, which corresponds to a decoding path having a maximum likelihood probability from among decoding paths of the decoding path list, as an information word.
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公开(公告)号：US10438684B2
公开(公告)日：2019-10-08
申请号：US14696609
申请日：2015-04-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seong-Hyeog Choi , Jun-Jin Kong , Hong-Rak Son , Pil-Sang Yoon , Chang-Kyu Seol , Ki-Jun Lee
Abstract: A method of operating a memory system, having a non-volatile memory device, includes processing a response to a first request toward the memory device by using an original key, in response to the first request, generating and storing first parity data corresponding to the original key, and deleting the original key.
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