Abstract:
A storage system is provided. The storage system includes a storage device including a plurality of nonvolatile memories configured to transmit storage throughput information, and a host device configured to change connection configurations for the storage device based on the storage throughput information, wherein the host device changes the connection configurations by changing configurations for transmitter and receiver paths between the storage device and the host device independently.
Abstract:
An eMMC includes flash memory including an extended card specific data (CSD) register (“EXT_CSD register”), and an eMMC controller that controls operation of the flash memory. The eMMC controller is receives a clock from a host via a clock line, receives a SEND_EXT_CSD command from the host via a command line, and provides the host with eMMC information stored in the EXT_CSD register via a data bus in response to the SEND_EXT_CSD command, the eMMC information including maximum operating frequency information for the eMMC.
Abstract:
An embedded multimedia card (eMMC) includes a clock channel that receives a clock signal from a host, a command channel that receives a command from the host, a plurality of data channels that transmit data to the host, and a return clock channel that transmits a return clock synchronized with the data to the host.
Abstract:
An embedded multimedia card (eMMC) includes a clock channel receiving a clock from a host, a complementary clock channel receiving a complementary clock from the host, a command/response channel exchanging commands/responses with the host, a plurality of data channels exchanging data between the host and the eMMC, a return clock channel sending a return clock to the host synchronously with data, a complementary return clock channel sending a complementary return clock to the host, and a reference voltage channel that either receives a reference voltage from the host or communicates a reference voltage to the host.
Abstract:
An embedded multimedia card (eMMC) includes a flash memory and an eMMC controller that controls operation of the flash memory. The eMMC controller includes a command register that receives from a host a command set defining a next operation specifying second data simultaneously with a transfer of first data specified by a current operation, a first memory that stores the first data, and a second memory that stores the second data.
Abstract:
An embedded multimedia card (eMMC) comprises a clock channel configured to receive a clock signal from a host, a command channel configured to receive a command from the host, a plurality of data channels configured to transmit data to the host, a data strobe channel configured to transmit a data strobe signal synchronized with the data to the host, and a data strobe control unit configured to selectively enable or generate the data strobe signal according to a protocol control signal.
Abstract:
An embedded multimedia card (eMMC) communicating with a host includes; a latch circuit that receives and latches a data signal according to either a first edge or a second edge of a clock to thereby generate a latched data signal, and a start bit detector that detects in the latched data signal a start bit and provides a valid data signal from a portion of the latched data signal following the start bit.