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公开(公告)号:US20240087976A1
公开(公告)日:2024-03-14
申请号:US18243437
申请日:2023-09-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Youngdeuk Kim , Mina Choi
IPC: H01L23/36 , H01L23/00 , H01L23/42 , H01L25/065 , H10B80/00
CPC classification number: H01L23/36 , H01L23/42 , H01L24/32 , H01L25/0652 , H10B80/00 , H01L24/16 , H01L24/33 , H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/73204 , H01L2224/73253 , H01L2225/06589
Abstract: Provided is a semiconductor package including a first substrate, a first chip structure on the first substrate, the first chip structure including at least one chip, a heat dissipation member on the first chip structure, the heat dissipation member including a heat dissipation plate including a first surface facing the first chip structure and a second surface opposite to the first surface and a seed metal layer on the second surface of the heat dissipation plate, and a metal thermal interfacial material (TIM) on the seed metal layer.
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公开(公告)号:US20240136340A1
公开(公告)日:2024-04-25
申请号:US18215212
申请日:2023-06-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Mina Choi , Heejung Hwang
IPC: H01L25/10 , H01L23/00 , H01L23/31 , H01L23/48 , H01L23/498
CPC classification number: H01L25/105 , H01L23/3128 , H01L23/481 , H01L23/49816 , H01L23/49822 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L2224/16227 , H01L2224/29186 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204
Abstract: A first package structure including a first redistribution structure, at least one first semiconductor chip disposed on the first redistribution structure, a first encapsulant covering the at least one first semiconductor chip, and a first through-via passing through the first encapsulant; a second package structure including a second redistribution structure, at least one second semiconductor chip disposed on the second redistribution structure, a second encapsulant covering the at least one second semiconductor chip, and a second through-via passing through the second encapsulant. The second package structure is disposed on the first package structure. At least one of a first upper end of the first through-via or a second upper end of the second through-via is between a first non-active surface and a second non-active surface.
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公开(公告)号:US20240234388A9
公开(公告)日:2024-07-11
申请号:US18215212
申请日:2023-06-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Mina Choi , Heejung Hwang
IPC: H01L25/10 , H01L23/00 , H01L23/31 , H01L23/48 , H01L23/498
CPC classification number: H01L25/105 , H01L23/3128 , H01L23/481 , H01L23/49816 , H01L23/49822 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L2224/16227 , H01L2224/29186 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204
Abstract: A first package structure including a first redistribution structure, at least one first semiconductor chip disposed on the first redistribution structure, a first encapsulant covering the at least one first semiconductor chip, and a first through-via passing through the first encapsulant; a second package structure including a second redistribution structure, at least one second semiconductor chip disposed on the second redistribution structure, a second encapsulant covering the at least one second semiconductor chip, and a second through-via passing through the second encapsulant. The second package structure is disposed on the first package structure. At least one of a first upper end of the first through-via or a second upper end of the second through-via is between a first non-active surface and a second non-active surface.
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公开(公告)号:US20230395459A1
公开(公告)日:2023-12-07
申请号:US18305726
申请日:2023-04-24
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sunggu Kang , Youngdeuk Kim , Mina Choi
IPC: H01L23/367 , H01L25/16 , H10B80/00 , H01L23/00 , H01L23/498
CPC classification number: H01L23/3675 , H01L25/162 , H01L25/165 , H10B80/00 , H01L24/16 , H01L24/32 , H01L24/73 , H01L23/49816 , H01L23/49833 , H01L23/49838 , H01L2924/1431 , H01L2924/1434 , H01L2224/16145 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204
Abstract: A semiconductor package includes: a first semiconductor chip on a first package substrate; a second semiconductor chip on a second package substrate; an interposer between the first semiconductor chip and the second package substrate; and a heat dissipation layer on the interposer, wherein the first and second semiconductor chips are spaced apart from each other horizontally and do not overlap in a vertical direction, and wherein a first portion of the heat dissipation layer at least partially overlapping the first semiconductor chip in the vertical direction and a second portion of the heat dissipation layer at least partially overlapping the second semiconductor chip in the vertical direction are spaced apart from each other, and the first portion is positioned around an outer boundary of the second portion.
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