公开(公告)号：US20200027875A1

公开(公告)日：2020-01-23

申请号：US16257464

申请日：2019-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seul-ki HONG ,  Hwi-chan JUN ,  Hyun-soo KIM ,  Dae-chul AHN ,  Myung YANG

IPC: H01L27/07 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/768 ,  H01L23/31 ,  H01L49/02 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes a substrate including a first region and a second region, an active gate structure on the substrate in the first region, a dummy gate structure on the substrate in the second region, a source/drain on the substrate in the first region at each of opposite sides of the active gate structure, a plurality of first conductive contacts respectively connected to the active gate structure and the source/drain, a resistive structure on the dummy gate structure in the second region, a plurality of second conductive contacts respectively connected to the plurality of first conductive contacts and the resistive structure, and an etch stop layer between the dummy gate structure and the resistive structure. The etch stop layer includes a lower etch stop layer and an upper etch stop layer, which are formed of different materials.

公开(公告)号：US20240162309A1

公开(公告)日：2024-05-16

申请号：US18135530

申请日：2023-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung YANG ,  Myunghoon JUNG ,  Seungmin SONG ,  Seungchan YUN ,  Sejung PARK ,  Kang-ill SEO

IPC: H01L29/417 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L21/8221 ,  H01L21/823871 ,  H01L27/0922 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Provided is a three-dimensional field-effect transistor (3DSFET) device including: a 1st source/drain region on a substrate, and a 2nd source/drain region on the 1st source/drain region; and a 1st source/drain contact structure on the 1st source/drain region, and a 2nd source/drain contact structure on the 2nd source/drain region, wherein the 2nd source/drain region is isolated from the 1st source/drain region through an interlayer structure, and wherein a spacer is formed at an upper portion of a sidewall of the 2nd source/drain contact structure, between the 1st source/drain contact structure and the 2nd source/drain contact structure.

公开(公告)号：US20250142871A1

公开(公告)日：2025-05-01

申请号：US18617125

申请日：2024-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehong LEE ,  Jintae KIM ,  Myung YANG ,  Kang-ill SEO

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Provided is a semiconductor device which includes a 1st source/drain region; and a 1st contact structure on a 1st portion of the 1st source/drain region; and a 2nd contact structure on a 2nd portion of the 1st source/drain region, wherein at least one of the 1st contact structure and the 2nd contact structure is configured to connect the 1st source/drain region to a voltage source or another circuit element for signal routing.

公开(公告)号：US20180068889A1

公开(公告)日：2018-03-08

申请号：US15624783

申请日：2017-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghun CHOI ,  Jeong Ik KIM ,  Myung YANG ,  Chul Sung KIM ,  Sang Jin HYUN

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/535

CPC classification number: H01L21/76862 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/535

Abstract: A semiconductor device and a method of manufacturing the same, the semiconductor device including a substrate; an insulating layer on the substrate, the insulating layer including a first trench and a second trench therein, the second trench having an aspect ratio that is smaller than an aspect ratio of the first trench; a barrier layer in the first trench and the second trench; a seed layer on the barrier layer in the first trench and the second trench; a first bulk layer on the seed layer and filled in the first trench; and a second bulk layer on the seed layer and filled in the second trench, wherein an average grain size of the second bulk layer is larger than an average grain size of the first bulk layer.