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    ELECTRONIC DEVICE AND OPERATING METHOD OF ELECTRONIC DEVICE
    1.
    发明公开
    ELECTRONIC DEVICE AND OPERATING METHOD OF ELECTRONIC DEVICE 审中-公开

    公开(公告)号：US20230215028A1

    公开(公告)日：2023-07-06

    申请号：US17949439

    申请日：2022-09-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang Woo KIM ,  Bum Jun KIM

    IPC: G06T7/55 ,  H04N13/243

    CPC classification number: G06T7/55 ,  H04N13/243 ,  G06T2207/20081 ,  G06T2207/20224 ,  H04N2013/0081

    Abstract: Disclosed is an operating method of an electronic device which includes a processor performing machine learning of a monocular depth estimation module. The operating method includes obtaining, by the processor, a first image and a second image respectively photographed by a first camera and a second camera of different locations, inferring, by the processor, a plurality of multi-cyclic disparities by applying weights of the monocular depth estimation module to the first image plural times and calculating a plurality of multi-cyclic loss functions based on the first image, the second image, and the plurality of multi-cyclic disparities, and updating, by the processor, the weights of the monocular depth estimation module through machine learning, based on the plurality of multi-cyclic loss functions.

    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM 审中-公开

    公开(公告)号：US20190214989A1

    公开(公告)日：2019-07-11

    申请号：US16107424

    申请日：2018-08-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yoo Seok SHON ,  Sang Woo KIM ,  Byung Tak LEE ,  Yun Ju KWON ,  Joon-Woo CHO

    IPC: H03K19/00 ,  G06F1/06 ,  G06F1/32

    Abstract: Provided are a semiconductor device and a semiconductor system. A semiconductor device includes a hardware auto clock gating (HWACG) logic configured to provide clock gating of an intellectual property (IP) block; and a memory power controller configured to perform power gating of a memory electrically connected with the IP block, based on the HWACG logic providing the clock gating for the IP block. The HWACG logic includes a first clock source configured to provide a first clock signal; a second clock source configured to receive the first clock signal provided by the first clock source, and provide a second clock signal to the IP block; a first clock control circuit configured to control the first clock source; and a second clock control circuit configured to transmit a clock request to the first clock control circuit, and control the second clock source, based on an operation state of the IP block.

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