公开(公告)号：US10177149B2

公开(公告)日：2019-01-08

申请号：US15452203

申请日：2017-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Jung Kim ,  Young Suk Chai ,  Sang Yong Kim ,  Hoon Joo Na ,  Sang Jin Hyun

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/775

Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.

公开(公告)号：US11967595B2

公开(公告)日：2024-04-23

申请号：US17038964

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Jung Kim ,  Young Suk Chai ,  Sang Yong Kim ,  Hoon Joo Na ,  Sang Jin Hyun

IPC: H01L27/092 ,  B82Y10/00 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L27/0924 ,  B82Y10/00 ,  H01L21/02603 ,  H01L21/823821 ,  H01L21/823842 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/7845

Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.

公开(公告)号：US12062706B2

公开(公告)日：2024-08-13

申请号：US17503764

申请日：2021-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Jung Kim ,  Sang Yong Kim ,  Byoung Hoon Lee ,  Chan Hyeong Lee

IPC: H01L29/423 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L29/0673

Abstract: A semiconductor device includes an active pattern disposed on a substrate. A gate insulating film is disposed on the active pattern and extends along the active pattern. A work function adjustment pattern is disposed on the gate insulating film and extends along the gate insulating film. A gate electrode is disposed on the work function adjustment pattern. The work function adjustment pattern includes a first work function adjustment film, a second work function adjustment film that includes aluminum and wraps the first work function adjustment film, and a barrier film including titanium silicon nitride (TiSiN). A silicon concentration of the barrier film is in a range of about 30 at % or less.

公开(公告)号：US10600913B2

公开(公告)日：2020-03-24

申请号：US16100804

申请日：2018-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won Keun Chung ,  Jong Ho Park ,  Seung Ha Oh ,  Sang Yong Kim ,  Hoon Joo Na ,  Sang Jin Hyun

IPC: H01L29/78 ,  H01L29/775 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  B82Y10/00 ,  H01L29/786 ,  H01L29/49 ,  H01L29/51 ,  H01L21/283 ,  H01L21/324

Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes first and second gate stack structures formed in first and second regions, respectively, wherein the first gate stack structure is formed adjacent a first channel region and comprises a first gate insulating film having a first thickness formed on the first channel region, a first function film having a second thickness formed on the first gate insulating film and a first filling film having a third thickness formed on the first function film, wherein the second gate stack structure is formed adjacent a second channel region and comprises a second gate insulating film having the first thickness formed on the second channel region, a second function film having the second thickness formed on the second gate insulating film and a second filling film having the third thickness formed on the second function film, wherein the first and second function films, respectively, comprise TiN and Si concentrations that are different from each other.