公开(公告)号：US20200350329A1

公开(公告)日：2020-11-05

申请号：US16690929

申请日：2019-11-21

Applicant: Samsung Electronics Co, Ltd.

Inventor： Kohji KANAMORI ,  Seogoo KANG ,  Shinhwan KANG

IPC: H01L27/11582 ,  H01L29/417

Abstract: A semiconductor memory device including a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer between the first and second semiconductor layers, gate electrodes arranged on the second semiconductor layer and spaced apart from each other in a first direction perpendicular to an upper surface of the second semiconductor layer, and channel structures penetrating the first, second and third semiconductor layers and the gate electrodes, each respective channel structure of channel structures including a gate insulating film, a channel layer, and a buried insulating film, the gate insulating film including a tunnel insulating film adjacent to the channel layer, a charge blocking film adjacent to the gate electrodes, and a charge storage film between the tunnel insulating film and the charge blocking film, and the charge storage film including an upper cover protruding toward the outside of the respective channel structure.

公开(公告)号：US20210375924A1

公开(公告)日：2021-12-02

申请号：US17400224

申请日：2021-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji KANAMORI ,  Seogoo KANG ,  Shinhwan KANG

IPC: H01L27/11582 ,  H01L29/417

Abstract: A semiconductor memory device including a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer between the first and second semiconductor layers, gate electrodes arranged on the second semiconductor layer and spaced apart from each other in a first direction perpendicular to an upper surface of the second semiconductor layer, and channel structures penetrating the first, second and third semiconductor layers and the gate electrodes, each respective channel structure of channel structures including a gate insulating film, a channel layer, and a buried insulating film, the gate insulating film including a tunnel insulating film adjacent to the channel layer, a charge blocking film adjacent to the gate electrodes, and a charge storage film between the tunnel insulating film and the charge blocking film, and the charge storage film including an upper cover protruding toward the outside of the respective channel structure.

公开(公告)号：US20210013304A1

公开(公告)日：2021-01-14

申请号：US16701427

申请日：2019-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojoon RYU ,  Kiyoon KANG ,  Seogoo KANG ,  Shinhwan KANG ,  Jesuk MOON ,  Byunggon PARK ,  Jaeryong SIM ,  Jinsoo LIM ,  Jisung CHEON ,  Jeehoon HAN

IPC: H01L29/06 ,  H01L23/31 ,  G11C5/06 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor device including a substrate having a cell, peripheral, and boundary area; a stack structure on the cell area and including insulating and interconnection layers that are alternately stacked; a molding layer on the peripheral area boundary areas; a selection line isolation pattern extending into the stack structure; a cell channel structure passing through the stack structure; and first dummy patterns extending into the molding layer on the peripheral area, wherein upper surfaces of the first dummy patterns, an upper surface of the selection line isolation pattern, and an upper surface of the cell channel structure are coplanar, and at least one of the first dummy patterns extends in parallel with the selection line isolation pattern or cell channel structure from upper surfaces of the first dummy patterns, the upper surface of the selection line isolation pattern, and the upper surface of the cell channel structure toward the substrate.

公开(公告)号：US20230061301A1

公开(公告)日：2023-03-02

申请号：US17857273

申请日：2022-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungdong KIM ,  Seogoo KANG ,  Kohji KANAMORI ,  Jeehoon HAN

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L23/528

Abstract: A semiconductor device includes an upper structure on a lower structure. The upper structure includes a stack structure including gate layers, a vertical memory structure penetrating the stack structure, a bit line electrically connected to the vertical memory structure and below the stack structure, and a conductive pattern electrically connected to the vertical memory structure and on the stack structure. The vertical memory structure includes an insulating core region, a first pad pattern electrically connected to the conductive pattern on the insulating core region, a dielectric structure on a side surface of the insulating core region and a side surface of the first pad pattern, and a channel layer. The channel layer includes a first portion contacting the dielectric structure and a second portion extending from the first portion and between a lower surface of the first pad pattern and an upper surface of the insulating core region.

公开(公告)号：US20210098483A1

公开(公告)日：2021-04-01

申请号：US16890500

申请日：2020-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seogoo KANG ,  Daehyun JANG ,  Jaeryong SIM ,  Jongseon AHN ,  Jeehoon HAN

IPC: H01L27/11575 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11548

Abstract: A semiconductor device includes a peripheral circuit region including a first substrate and circuit elements on the first substrate; and a memory cell region including a second substrate on an upper portion of the first substrate, gate electrodes spaced apart from each other and vertically stacked on the second substrate, channel structures extending vertically through the gate electrodes to the second substrate, first separation regions penetrating through the gate electrodes between the channel structures and extending in one direction, and a second separation region extending vertically to penetrate through the second substrate from above and having a bent portion due to a change in width.

公开(公告)号：US20210066344A1

公开(公告)日：2021-03-04

申请号：US16850244

申请日：2020-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younghwan SON ,  Seungwon LEE ,  Seogoo KANG ,  Juyoung LIM ,  Jeehoon HAN

IPC: H01L27/11582 ,  H01L29/51 ,  H01L29/49 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11565 ,  G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G11C11/56

Abstract: A vertical non-volatile memory device includes a channel on a substrate and extending in a first direction perpendicular to an upper surface of the substrate, a first charge storage structure on an outer sidewall of the channel, a second charge storage structure on an inner sidewall of the channel, first gate electrodes spaced apart from each other in the first direction on the substrate, each which surrounds the first charge storage structure, and a second gate electrode on an inner sidewall of the second charge storage structure.

公开(公告)号：US20210036011A1

公开(公告)日：2021-02-04

申请号：US16844429

申请日：2020-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghwan SON ,  Seogoo KANG ,  Jeehoon HAN

IPC: H01L27/11582 ,  G11C8/14 ,  G11C7/18 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L29/423

Abstract: A semiconductor device is disclosed. The semiconductor device includes a channel structure on a substrate and extending in a first direction perpendicular to a top surface of the substrate; a plurality of gate electrodes on the substrate and spaced apart from one another in the first direction on a sidewall of the channel structure; and a gate insulating layer between each of the plurality of gate electrodes and the channel structure, wherein the channel structure includes a body gate layer extending in the first direction; a charge storage structure surrounding a sidewall of the body gate layer; and a channel layer surrounding sidewall of the charge storage structure.