Micro LED display including antistatic ground circuit board

    公开(公告)号:US12119370B2

    公开(公告)日:2024-10-15

    申请号:US17535800

    申请日:2021-11-26

    CPC classification number: H01L27/156 H01L27/0248 H05K9/0054 H05K9/0067

    Abstract: An antistatic ground circuit board and a micro light emitting diode (LED) display including same are provided. The display includes a substrate comprising a first surface oriented toward a first direction, a second surface oriented toward a second direction opposite the first direction, and a side surface oriented toward a third direction perpendicular to the first and second directions, a first circuit unit disposed on the first surface, a second circuit unit disposed on the second surface, a side circuit unit disposed on the side surface and electrically connected to the first circuit unit, a plurality of micro LED chips arranged on one surface of the first circuit unit oriented toward the first direction, and a ground circuit board disposed on the second surface to ground static electricity generated in one or more circuit units from among the first circuit unit, the second circuit unit, and the side circuit unit.

    Display panel and display apparatus having the same

    公开(公告)号:US12260790B2

    公开(公告)日:2025-03-25

    申请号:US17942775

    申请日:2022-09-12

    Abstract: A display panel in which a resistance structure is provided on a test pattern to prevent a circuit of the display panel from being damaged by static electricity introduced into the test pattern, and a display apparatus having the same are provided. The display panel includes: a substrate; a plurality of pixel circuits provided on the substrate and configured to drive a plurality of inorganic light emitting devices; a test line provided on the substrate and extending from an edge of the substrate; an insulating layer provided on the test line; and a resistance structure provided on the test line, the resistance structure including: at least two vertical interconnect accesses (vias) passing through the insulating layer, and a resistance layer provided on the insulating layer and extending between the at least two vias, wherein the at least two vias connect the test line and the resistance layer to each other, and the test line is discontinuous at an area between the at least two vias, and wherein the resistance layer is configured to receive, through one of the at least two vias, a current applied to the test line.

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