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公开(公告)号：US09437526B2
公开(公告)日：2016-09-06
申请号：US14259200
申请日：2014-04-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： So-Young Lim , Na-Rae Shin , Jeong-Kyu Ha , Kyoung-Suk Yang , Pa-Lan Lee
IPC: H01L23/498 , H01L23/495 , H01L23/482 , H05K1/11 , H01L23/00
CPC classification number: H01L23/49541 , H01L23/00 , H01L23/4824 , H01L23/49838 , H01L23/4985 , H01L24/16 , H01L2224/16225 , H05K1/118
Abstract: A chip on film (COF) package includes a film substrate, first leads on a first surface of the film substrate, the first leads having a first length, and second leads on the first surface of the film substrate, the second leads having a second length larger than the first length, first via plugs penetrating the film substrate and connected to first ends of the first leads, and second via plugs penetrating the film substrate and connected to first ends of the second leads, and first connection leads on a second surface of the film substrate facing the first surface, the first connection leads having first ends connected to the first via plugs, and second connection leads on the second surface of the film substrate, the second connection leads having first ends electrically connected to the second via plugs.
Abstract translation: 膜芯片（COF）封装包括薄膜基板，第一引线在薄膜基板的第一表面上，第一引线具有第一长度，第二引线在薄膜基板的第一表面上，第二引线具有第二引线 长度大于第一长度，首先通过插入薄膜基板并连接到第一引线的第一端的插塞，以及穿过薄膜基片并连接到第二引线的第一端的第二通孔塞，第二表面上的第一连接引线 所述第一连接引线具有连接到所述第一通孔的第一端和所述薄膜基板的第二表面上的第二连接引线，所述第二连接引线具有电连接到所述第二通孔塞 。
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Patent Agency Ranking
公开(公告)号：US09869717B2
公开(公告)日：2018-01-16
申请号：US15218515
申请日：2016-07-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： So-Young Lim , Sang-Heui Lee
CPC classification number: G01R31/2884 , G01R1/06 , G09G3/006 , H01L22/32 , H01L23/4985 , H01L2924/0002 , H05K1/0268 , H05K1/189 , H05K3/0052 , H05K2201/10681 , H01L2924/00
Abstract: A test pad structure includes a plurality of test pads and a plurality of connection leads. The test pads are sequentially arranged from a wiring pattern on a substrate and in rows parallel with one another. The test pads include first and second groups of test pads, the first group having at least one pad and the second group having at least two pads. The connection leads extend from end portions of the wiring pattern to be connected to the test pads. The connection leads include at least one inner lead passing between the at least two pads of the second group and arranged in a first row closest to the first group. The at least one inner lead may be connected to at least one pad of the at least two pads of the second group arranged in a second row next to the first row.
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3.发明申请Chip on Film (COF) Substrate, COF Package and Display Device Including the Same 有权芯片贴片（COF）衬底，包括它的COF封装和显示设备公开(公告)号：US20140054793A1
公开(公告)日：2014-02-27
申请号：US13933185
申请日：2013-07-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jeong-Kyu Ha , Kwan-Jai Lee , Jae-Min Jung , Kyong-Soon Cho , Na-Rae Shin , Kyoung-Suk Yang , Pa-Lan Lee , So-Young Lim
IPC: H01L23/498
CPC classification number: H01L23/49838 , H01L23/4985 , H01L2924/0002 , H01L2924/00
Abstract: A COF substrate may include a base film, first upper conductive patterns, at least one second upper conductive pattern and lower conductive patterns. The first upper conductive patterns may be arranged on an upper surface of the base film. Each of the first upper conductive patterns may have an inner pattern and an outer pattern spaced apart from each other. The second upper conductive pattern may be arranged on the upper surface of the base film between the first upper conductive patterns. The lower conductive patterns may be arranged on a lower surface of the base film. The lower conductive patterns may be electrically connected between the inner pattern and the outer pattern. Thus, conductive materials causing a short between the panel patterns may not exist between the inner pattern and the outer pattern on the upper surface of the base film.
Abstract translation: COF基板可以包括基膜，第一上导电图案，至少一个第二上导电图案和下导电图案。 第一上导电图案可以布置在基膜的上表面上。 每个第一上导电图案可以具有彼此间隔开的内图案和外图案。 第二上导电图案可以布置在第一上导电图案之间的基膜的上表面上。 下导电图案可以布置在基膜的下表面上。 下部导电图案可以电连接在内部图案和外部图案之间。 因此，在基片的上表面上的内图案和外图案之间可能不存在在面板图案之间引起短路的导电材料。
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公开(公告)号：US09280182B2
公开(公告)日：2016-03-08
申请号：US14195352
申请日：2014-03-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeong-Kyu Ha , Kwan-Jai Lee , Jae-Min Jung , Kyong-Soon Cho , Na-Rae Shin , Kyoung-Suk Yang , Pa-Lan Lee , So-Young Lim
CPC classification number: G06F3/0412 , G06F1/1626 , G06F1/1637 , G06F1/1643 , G06F1/1652 , G06F3/0416 , G06F2203/04102 , H01L27/323 , H01L27/3276 , H01L2251/5338
Abstract: A chip on film package includes a flexible base film having a first surface and a second surface opposite to each other that includes at least one through hole therein, a plurality of wirings disposed on the first surface and the second surface of the base film, respectively, that include a first lead and a second lead connected to each other through the at least one through hole, and a display panel driving chip and a touch panel sensor chip, each mounted on any one of the first surface and the second surface of the base film, wherein at least one of the display panel driving panel and the touch panel sensor chip is electrically connected to the first and second leads.
Abstract translation: 薄膜封装上的芯片包括柔性基膜，其具有彼此相对的第一表面和第二表面，所述第一表面和第二表面在其中包括至少一个通孔，分别设置在基膜的第一表面和第二表面上的多个布线 ，其包括通过所述至少一个通孔彼此连接的第一引线和第二引线，以及显示面板驱动芯片和触摸面板传感器芯片，每个安装在所述第一引线和所述第二表面中的任何一个上 其中所述显示面板驱动面板和所述触摸面板传感器芯片中的至少一个电连接到所述第一和第二引线。
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5.发明授权Chip on film (COF) substrate, COF package and display device including the same 有权贴膜（COF）基板，COF封装和包括其的显示装置公开(公告)号：US09059162B2
公开(公告)日：2015-06-16
申请号：US13933185
申请日：2013-07-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jeong-Kyu Ha , Kwan-Jai Lee , Jae-Min Jung , Kyong-Soon Cho , Na-Rae Shin , Kyoung-Suk Yang , Pa-Lan Lee , So-Young Lim
IPC: H01L23/498
CPC classification number: H01L23/49838 , H01L23/4985 , H01L2924/0002 , H01L2924/00
Abstract: A COF substrate may include a base film, first upper conductive patterns, at least one second upper conductive pattern and lower conductive patterns. The first upper conductive patterns may be arranged on an upper surface of the base film. Each of the first upper conductive patterns may have an inner pattern and an outer pattern spaced apart from each other. The second upper conductive pattern may be arranged on the upper surface of the base film between the first upper conductive patterns. The lower conductive patterns may be arranged on a lower surface of the base film. The lower conductive patterns may be electrically connected between the inner pattern and the outer pattern. Thus, conductive materials causing a short between the panel patterns may not exist between the inner pattern and the outer pattern on the upper surface of the base film.
Abstract translation: COF基板可以包括基膜，第一上导电图案，至少一个第二上导电图案和下导电图案。 第一上导电图案可以布置在基膜的上表面上。 每个第一上导电图案可以具有彼此间隔开的内图案和外图案。 第二上导电图案可以布置在第一上导电图案之间的基膜的上表面上。 下导电图案可以布置在基膜的下表面上。 下部导电图案可以电连接在内部图案和外部图案之间。 因此，在基片的上表面上的内图案和外图案之间可能不存在在面板图案之间引起短路的导电材料。
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公开(公告)号：US20140246687A1
公开(公告)日：2014-09-04
申请号：US14195352
申请日：2014-03-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeong-Kyu Ha , Kwan-Jai Lee , Jae-Min Jung , Kyong-Soon Cho , Na-Rae Shin , Kyoung-Suk Yang , Pa-Lan Lee , So-Young Lim
IPC: H01L27/32
CPC classification number: G06F3/0412 , G06F1/1626 , G06F1/1637 , G06F1/1643 , G06F1/1652 , G06F3/0416 , G06F2203/04102 , H01L27/323 , H01L27/3276 , H01L2251/5338
Abstract: A chip on film package includes a flexible base film having a first surface and a second surface opposite to each other that includes at least one through hole therein, a plurality of wirings disposed on the first surface and the second surface of the base film, respectively, that include a first lead and a second lead connected to each other through the at least one through hole, and a display panel driving chip and a touch panel sensor chip, each mounted on any one of the first surface and the second surface of the base film, wherein at least one of the display panel driving panel and the touch panel sensor chip is electrically connected to the first and second leads.
Abstract translation: 薄膜封装上的芯片包括柔性基膜，其具有彼此相对的第一表面和第二表面，所述第一表面和第二表面在其中包括至少一个通孔，分别设置在基膜的第一表面和第二表面上的多个布线 ，其包括通过所述至少一个通孔彼此连接的第一引线和第二引线，以及显示面板驱动芯片和触摸面板传感器芯片，每个安装在所述第一引线和所述第二表面中的任何一个上 其中所述显示面板驱动面板和所述触摸面板传感器芯片中的至少一个电连接到所述第一和第二引线。
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