公开(公告)号：US08952510B2

公开(公告)日：2015-02-10

申请号：US14061784

申请日：2013-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Sang Cho ,  Chang-Sig Kang ,  Dae-Woo Son ,  Yun-Seok Choi ,  Kyong-Soon Cho ,  Sang-Heui Lee

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L24/50 ,  H01L23/4985 ,  H01L24/06 ,  H01L2224/0401 ,  H01L2224/0405 ,  H01L2224/05553 ,  H01L2224/06155 ,  H01L2224/14155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14

Abstract: A semiconductor chip for a TAB package includes a surface including a set of input pads connected to internal circuitry of the chip and for receiving external signals The surface includes output pads. A plurality of input pads are adjacent a first edge and are in a first row substantially parallel to the first edge and extending in a first direction; a plurality of first output pads are adjacent a second edge, and are in a second row substantially parallel to the second edge and extending in the first direction; and a plurality of second output pads are located between the first row and the second row. The plurality of second output pads include first and second outermost pads located a certain distance from a respective third edge and fourth edge, and first and second inner pads located a greater distance from the respective third edge and fourth edge.

Abstract translation: 用于TAB封装的半导体芯片包括包括连接到芯片的内部电路并用于接收外部信号的一组输入焊盘的表面。该表面包括输出焊盘。 多个输入焊盘与第一边缘相邻并且处于基本上平行于第一边缘并沿第一方向延伸的第一行; 多个第一输出焊盘与第二边缘相邻，并且处于基本上平行于第二边缘并沿第一方向延伸的第二行; 并且多个第二输出焊盘位于第一行和第二行之间。 多个第二输出焊盘包括位于距相应的第三边缘和第四边缘一定距离的第一和第二最外面的焊盘，以及第一和第二内部焊盘位于距相应的第三边缘和第四边缘更大的距离处。

公开(公告)号：US20140084430A1

公开(公告)日：2014-03-27

申请号：US14061784

申请日：2013-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Sang Cho ,  Chang-Sig Kang ,  Dae-Woo Son ,  Yun-Seok Choi ,  Kyong-Soon Cho ,  Sang-Heui Lee

IPC: H01L23/00

CPC classification number: H01L24/50 ,  H01L23/4985 ,  H01L24/06 ,  H01L2224/0401 ,  H01L2224/0405 ,  H01L2224/05553 ,  H01L2224/06155 ,  H01L2224/14155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14

Abstract: A semiconductor chip for a TAB package includes a surface including a set of input pads connected to internal circuitry of the chip and for receiving external signals The surface includes output pads. A plurality of input pads are adjacent a first edge and are in a first row substantially parallel to the first edge and extending in a first direction; a plurality of first output pads are adjacent a second edge, and are in a second row substantially parallel to the second edge and extending in the first direction; and a plurality of second output pads are located between the first row and the second row. The plurality of second output pads first and second outermost pads located a certain distance from a respective third edge and fourth edge, and first and second inner pads located a greater distance from the respective third edge and fourth edge.

Abstract translation: 用于TAB封装的半导体芯片包括包括连接到芯片的内部电路并用于接收外部信号的一组输入焊盘的表面。该表面包括输出焊盘。 多个输入焊盘与第一边缘相邻并且处于基本上平行于第一边缘并沿第一方向延伸的第一行; 多个第一输出焊盘与第二边缘相邻，并且处于基本上平行于第二边缘并沿第一方向延伸的第二行; 并且多个第二输出焊盘位于第一行和第二行之间。 多个第二输出焊盘第一和第二最外面焊盘位于相应的第三边缘和第四边缘一定距离处，并且第一和第二内部焊盘位于距相应的第三边缘和第四边缘更大的距离处。

公开(公告)号：US10105102B2

公开(公告)日：2018-10-23

申请号：US14703833

申请日：2015-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mitsuo Umemoto ,  Yung-Cheol Kong ,  Woon-Bae Kim ,  Pyoung-Wan Kim ,  Kyong-Soon Cho

IPC: A61B5/00 ,  A61B5/145 ,  A61B5/0215

Abstract: Provided is a body-implantable package for processing biosensed-data for wireless communication to an external device. The package includes a tube closed by a cover, therein, a chip with a strained layer affixed thereto to form a flexible laminar circuit. The cover is fitted over an open end of the tube after the laminated chip and strained layer are inserted therein. The chip is constructed of and rolled in one or more turns into a generally cylindrical shape. The strained layer is affixed to a surface of the chip automatically to cause the flexible laminar circuit to curl into a generally cylindrical shape to fit within the tube.

公开(公告)号：US09305990B2

公开(公告)日：2016-04-05

申请号：US14202167

申请日：2014-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Min Jung ,  Kyong-Soon Cho ,  Jeong-Kyu Ha

IPC: G02F1/1343 ,  G02F1/1345 ,  H01L27/32 ,  H01L23/498

CPC classification number: H01L27/3276 ,  G02F1/13452 ,  H01L23/4985 ,  H01L2224/16225 ,  H01L2924/12044 ,  H01L2924/00

Abstract: Provided are a chip-on-film (COF) package and a device assembly including the same. The device assembly includes a COF package including a film substrate on which a plurality of film-through wires are formed. The device assembly includes a panel unit including a panel substrate on which a plurality of panel-through wires are formed. The panel unit is disposed on the COF package. One end of the panel unit is electrically connected to a first end of the COF package. The device assembly includes a control unit disposed below the panel unit. One end of the control unit is electrically connected to a second end of the COF package.

Abstract translation: 提供了片上胶片（COF）包装和包括其的装置组件。 装置组件包括COF封装，其包括其上形成有多个胶片通孔的膜基板。 所述装置组件包括面板单元，所述面板单元包括其上形成有多个通孔导线的面板基板。 面板单元设置在COF包装上。 面板单元的一端电连接到COF封装的第一端。 设备组件包括设置在面板单元下方的控制单元。 控制单元的一端电连接到COF封装的第二端。

公开(公告)号：US20140054793A1

公开(公告)日：2014-02-27

申请号：US13933185

申请日：2013-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-Kyu Ha ,  Kwan-Jai Lee ,  Jae-Min Jung ,  Kyong-Soon Cho ,  Na-Rae Shin ,  Kyoung-Suk Yang ,  Pa-Lan Lee ,  So-Young Lim

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A COF substrate may include a base film, first upper conductive patterns, at least one second upper conductive pattern and lower conductive patterns. The first upper conductive patterns may be arranged on an upper surface of the base film. Each of the first upper conductive patterns may have an inner pattern and an outer pattern spaced apart from each other. The second upper conductive pattern may be arranged on the upper surface of the base film between the first upper conductive patterns. The lower conductive patterns may be arranged on a lower surface of the base film. The lower conductive patterns may be electrically connected between the inner pattern and the outer pattern. Thus, conductive materials causing a short between the panel patterns may not exist between the inner pattern and the outer pattern on the upper surface of the base film.

Abstract translation: COF基板可以包括基膜，第一上导电图案，至少一个第二上导电图案和下导电图案。 第一上导电图案可以布置在基膜的上表面上。 每个第一上导电图案可以具有彼此间隔开的内图案和外图案。 第二上导电图案可以布置在第一上导电图案之间的基膜的上表面上。 下导电图案可以布置在基膜的下表面上。 下部导电图案可以电连接在内部图案和外部图案之间。 因此，在基片的上表面上的内图案和外图案之间可能不存在在面板图案之间引起短路的导电材料。

公开(公告)号：US20130234310A1

公开(公告)日：2013-09-12

申请号：US13651752

申请日：2012-10-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Han-Shin Youn ,  Kyong-Soon Cho

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L23/36 ,  G01N29/0681 ,  H01L21/56 ,  H01L22/12 ,  H01L23/3128 ,  H01L23/3185 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29011 ,  H01L2224/32221 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/8385 ,  H01L2224/92225 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A flip chip package may include package substrate, a semiconductor chip, conductive bumps, a molding member and a heat sink. The semiconductor chip may be arranged over an upper surface of the package substrate. The conductive bumps may be interposed between a lower surface of the semiconductor chip and the upper surface of the package substrate to electrically connect the semiconductor chip and the package substrate with each other. The molding member may be formed on the upper surface of the package substrate to cover the semiconductor chip. The heat sink may make contact with the semiconductor chip to dissipate a heat in the semiconductor chip. An ultrasonic wave may pass through only one interface between the semiconductor chip and the molding member, so that scattering of the ultrasonic wave may be suppressed.

Abstract translation: 倒装芯片封装可以包括封装衬底，半导体芯片，导电凸块，模制构件和散热器。 半导体芯片可以布置在封装衬底的上表面上。 导电凸块可以插入在半导体芯片的下表面和封装基板的上表面之间，以将半导体芯片和封装基板彼此电连接。 模制构件可以形成在封装衬底的上表面上以覆盖半导体芯片。 散热器可以与半导体芯片接触以在半导体芯片中散热。 超声波可以仅穿过半导体芯片和模制构件之间的一个界面，从而可以抑制超声波的散射。

公开(公告)号：US09280182B2

公开(公告)日：2016-03-08

申请号：US14195352

申请日：2014-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeong-Kyu Ha ,  Kwan-Jai Lee ,  Jae-Min Jung ,  Kyong-Soon Cho ,  Na-Rae Shin ,  Kyoung-Suk Yang ,  Pa-Lan Lee ,  So-Young Lim

IPC: H01L29/18 ,  G06F1/16 ,  G06F3/041 ,  H01L27/32

CPC classification number: G06F3/0412 ,  G06F1/1626 ,  G06F1/1637 ,  G06F1/1643 ,  G06F1/1652 ,  G06F3/0416 ,  G06F2203/04102 ,  H01L27/323 ,  H01L27/3276 ,  H01L2251/5338

Abstract: A chip on film package includes a flexible base film having a first surface and a second surface opposite to each other that includes at least one through hole therein, a plurality of wirings disposed on the first surface and the second surface of the base film, respectively, that include a first lead and a second lead connected to each other through the at least one through hole, and a display panel driving chip and a touch panel sensor chip, each mounted on any one of the first surface and the second surface of the base film, wherein at least one of the display panel driving panel and the touch panel sensor chip is electrically connected to the first and second leads.

Abstract translation: 薄膜封装上的芯片包括柔性基膜，其具有彼此相对的第一表面和第二表面，所述第一表面和第二表面在其中包括至少一个通孔，分别设置在基膜的第一表面和第二表面上的多个布线 ，其包括通过所述至少一个通孔彼此连接的第一引线和第二引线，以及显示面板驱动芯片和触摸面板传感器芯片，每个安装在所述第一引线和所述第二表面中的任何一个上 其中所述显示面板驱动面板和所述触摸面板传感器芯片中的至少一个电连接到所述第一和第二引线。

公开(公告)号：US09059162B2

公开(公告)日：2015-06-16

申请号：US13933185

申请日：2013-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-Kyu Ha ,  Kwan-Jai Lee ,  Jae-Min Jung ,  Kyong-Soon Cho ,  Na-Rae Shin ,  Kyoung-Suk Yang ,  Pa-Lan Lee ,  So-Young Lim

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A COF substrate may include a base film, first upper conductive patterns, at least one second upper conductive pattern and lower conductive patterns. The first upper conductive patterns may be arranged on an upper surface of the base film. Each of the first upper conductive patterns may have an inner pattern and an outer pattern spaced apart from each other. The second upper conductive pattern may be arranged on the upper surface of the base film between the first upper conductive patterns. The lower conductive patterns may be arranged on a lower surface of the base film. The lower conductive patterns may be electrically connected between the inner pattern and the outer pattern. Thus, conductive materials causing a short between the panel patterns may not exist between the inner pattern and the outer pattern on the upper surface of the base film.

Abstract translation: COF基板可以包括基膜，第一上导电图案，至少一个第二上导电图案和下导电图案。 第一上导电图案可以布置在基膜的上表面上。 每个第一上导电图案可以具有彼此间隔开的内图案和外图案。 第二上导电图案可以布置在第一上导电图案之间的基膜的上表面上。 下导电图案可以布置在基膜的下表面上。 下部导电图案可以电连接在内部图案和外部图案之间。 因此，在基片的上表面上的内图案和外图案之间可能不存在在面板图案之间引起短路的导电材料。

公开(公告)号：US20140246687A1

公开(公告)日：2014-09-04

申请号：US14195352

申请日：2014-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeong-Kyu Ha ,  Kwan-Jai Lee ,  Jae-Min Jung ,  Kyong-Soon Cho ,  Na-Rae Shin ,  Kyoung-Suk Yang ,  Pa-Lan Lee ,  So-Young Lim

IPC: H01L27/32

CPC classification number: G06F3/0412 ,  G06F1/1626 ,  G06F1/1637 ,  G06F1/1643 ,  G06F1/1652 ,  G06F3/0416 ,  G06F2203/04102 ,  H01L27/323 ,  H01L27/3276 ,  H01L2251/5338

Abstract: A chip on film package includes a flexible base film having a first surface and a second surface opposite to each other that includes at least one through hole therein, a plurality of wirings disposed on the first surface and the second surface of the base film, respectively, that include a first lead and a second lead connected to each other through the at least one through hole, and a display panel driving chip and a touch panel sensor chip, each mounted on any one of the first surface and the second surface of the base film, wherein at least one of the display panel driving panel and the touch panel sensor chip is electrically connected to the first and second leads.

Abstract translation: 薄膜封装上的芯片包括柔性基膜，其具有彼此相对的第一表面和第二表面，所述第一表面和第二表面在其中包括至少一个通孔，分别设置在基膜的第一表面和第二表面上的多个布线 ，其包括通过所述至少一个通孔彼此连接的第一引线和第二引线，以及显示面板驱动芯片和触摸面板传感器芯片，每个安装在所述第一引线和所述第二表面中的任何一个上 其中所述显示面板驱动面板和所述触摸面板传感器芯片中的至少一个电连接到所述第一和第二引线。