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公开(公告)号:US20210035976A1
公开(公告)日:2021-02-04
申请号:US16919300
申请日:2020-07-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Yeong Han GWON , Soo Yeon JEONG , Geum Jong BAE , Dong Il BAE
IPC: H01L27/092 , H01L23/535 , H01L29/423
Abstract: A semiconductor device includes a substrate, a first lower pattern and a second lower pattern on the substrate and arranged in a line in a first direction, a first active pattern stack disposed on and spaced apart from the first lower pattern, a second active pattern stack disposed on and spaced apart from the first lower pattern, a fin-cut gate structure disposed on the first lower pattern and overlapping a portion of the first lower pattern, a first gate structure surrounding the first active pattern stack and extending in a second direction crossing the first direction, a second gate structure surrounding the second active pattern stack and extending in the second direction, and a device isolation layer between the first gate structure and the second gate structure and separating the first lower pattern and the second lower pattern.
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公开(公告)号:US20190109214A1
公开(公告)日:2019-04-11
申请号:US16197752
申请日:2018-11-21
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kyung Yub JEON , Tae Yong KWON , Oh Seong KWON , Soo Yeon JEONG , Yong Hee PARK , Jong Ryeol YOO
IPC: H01L29/66 , H01L29/10 , H01L29/78 , H01L29/423
Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.
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公开(公告)号:US20180350952A1
公开(公告)日:2018-12-06
申请号:US15878711
申请日:2018-01-24
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kyung Yub JEON , Tae Yong KWON , Oh Seong KWON , Soo Yeon JEONG , Yong Hee PARK , Jong Ryeol YOO
IPC: H01L29/66 , H01L29/78 , H01L29/423 , H01L29/10
CPC classification number: H01L29/66666 , H01L29/1037 , H01L29/4238 , H01L29/66553 , H01L29/7827
Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.
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公开(公告)号:US20170365526A1
公开(公告)日:2017-12-21
申请号:US15290456
申请日:2016-10-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Soo Yeon JEONG , Myung Gil KANG
IPC: H01L21/8238 , H01L29/66 , H01L29/49 , H01L29/06 , H01L27/092 , H01L23/535 , H01L29/78 , H01L29/417
CPC classification number: H01L21/823821 , H01L21/823828 , H01L21/823885 , H01L23/535 , H01L27/092 , H01L27/0924 , H01L29/0649 , H01L29/41791 , H01L29/4966 , H01L29/66553 , H01L29/66666 , H01L29/66795 , H01L29/7827 , H01L29/785
Abstract: A vertical fin field effect transistor (V-FinFET) is provided as follows. A substrate has a lower source/drain (S/D). A fin structure extends vertically from an upper surface of the lower S/D. The fin structure includes a sidewall having an upper sidewall portion, a lower sidewall portion and a center sidewall portion positioned therebetween. An upper S/D is disposed on an upper surface of the fin structure. An upper spacer is disposed on the upper sidewall portion. A lower spacer is disposed on the lower sidewall portion. A stacked structure including a gate oxide layer and a first gate electrode is disposed on an upper surface of the lower spacer, the center sidewall portion and a lower surface of the upper spacer. A second gate electrode is disposed on the first gate electrode
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