公开(公告)号：US12046631B2

公开(公告)日：2024-07-23

申请号：US18065986

申请日：2022-12-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Sik Park ,  Sang Jin Kim ,  Tae Hwan Oh ,  Hyun Jeong Lee ,  Sung Jin Jang ,  Gyu Min Jeong

IPC: H01L27/01 ,  H01L21/762 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L31/0392 ,  H01L21/8234

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L29/6656 ,  H01L29/66795 ,  H01L21/823431

Abstract: A semiconductor device includes first and second active patterns extending in a first direction, a first epitaxial pattern on the first active pattern and adjacent to the second active pattern, a second epitaxial pattern on the second active pattern and adjacent to the first active pattern, an element separation structure separating the first and second active patterns between the first and second epitaxial patterns, and including a core separation pattern, and a separation side wall pattern on a side wall of the core separation pattern, and a gate structure extending in a second direction intersecting the first direction, on the first active pattern. An upper surface of the gate structure is on the same plane as an upper surface of the core separation pattern. The separation side wall pattern includes a high dielectric constant liner, which includes a high dielectric constant dielectric film including a metal.

公开(公告)号：US11552167B2

公开(公告)日：2023-01-10

申请号：US17363861

申请日：2021-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Sik Park ,  Sang Jin Kim ,  Tae Hwan Oh ,  Hyun Jeong Lee ,  Sung Jin Jang ,  Gyu Min Jeong

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L21/8234

Abstract: A semiconductor device includes first and second active patterns extending in a first direction, a first epitaxial pattern on the first active pattern and adjacent to the second active pattern, a second epitaxial pattern on the second active pattern and adjacent to the first active pattern, an element separation structure separating the first and second active patterns between the first and second epitaxial patterns, and including a core separation pattern, and a separation side wall pattern on a side wall of the core separation pattern, and a gate structure extending in a second direction intersecting the first direction, on the first active pattern. An upper surface of the gate structure is on the same plane as an upper surface of the core separation pattern. The separation side wall pattern includes a high dielectric constant liner, which includes a high dielectric constant dielectric film including a metal.

公开(公告)号：US10276373B2

公开(公告)日：2019-04-30

申请号：US15490976

申请日：2017-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong Chul Jeong ,  Tae Kyu Lee ,  Sung Sik Park ,  Joon Soo Park ,  Kwang Sub Yoon ,  Boo Hyun Ham

IPC: H01L21/027 ,  G03F7/09 ,  G03F7/075 ,  G03F7/42 ,  H01L21/311 ,  H01L21/266 ,  H01L21/768 ,  H01L21/8234

Abstract: A method for manufacturing a semiconductor device includes forming an etch target layer on a semiconductor substrate, forming a first photoresist pattern disposed on the etch target layer, irradiating ultraviolet (UV) light in an oxygen-containing atmosphere to remove the first photoresist pattern from the etch target layer, and forming a second photoresist pattern on the etch target layer.

公开(公告)号：US20220013630A1

公开(公告)日：2022-01-13

申请号：US17363861

申请日：2021-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Sik Park ,  Sang Jin Kim ,  Tae Hwan Oh ,  Hyun Jeong Lee ,  Sung Jin Jang ,  Gyu Min Jeong

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/762

Abstract: A semiconductor device includes first and second active patterns extending in a first direction, a first epitaxial pattern on the first active pattern and adjacent to the second active pattern, a second epitaxial pattern on the second active pattern and adjacent to the first active pattern, an element separation structure separating the first and second active patterns between the first and second epitaxial patterns, and including a core separation pattern, and a separation side wall pattern on a side wall of the core separation pattern, and a gate structure extending in a second direction intersecting the first direction, on the first active pattern. An upper surface of the gate structure is on the same plane as an upper surface of the core separation pattern. The separation side wall pattern includes a high dielectric constant liner, which includes a high dielectric constant dielectric film including a metal.

公开(公告)号：US10553429B2

公开(公告)日：2020-02-04

申请号：US15355360

申请日：2016-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Boo Hyun Ham ,  Hyun Jae Kang ,  Sung Sik Park ,  Yong Kug Bae ,  Kwang Sub Yoon ,  Bum Joon Youn ,  Hyun Chang Lee

IPC: H01L21/312 ,  H01L21/033 ,  H01L23/544

Abstract: A method of forming a pattern of a semiconductor device includes forming a mask and a sacrificial layer on a substrate, etching the sacrificial layer in a first area of the substrate to form first units, each having a first width and a first distance from an adjacent unit, etching the sacrificial layer in a second area of the substrate to form second units, each having a second width equal to the first distance and being spaced apart from an adjacent unit by a second distance equal to the first width, forming a spacer conformally covering the first and second units, the spacer having a first thickness and being merged between the second units, removing a portion of the spacer on upper surfaces of the first and second units, and etching the mask in a region from which first and second units have been removed.