公开(公告)号：US20180024879A1

公开(公告)日：2018-01-25

申请号：US15652521

申请日：2017-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Rae KIM ,  Gyu Yeol Kong ,  Ki Jun Lee ,  Jun Jin Kong ,  Hong Rak Son ,  Beom Kyu Shin ,  Heon Hwa Cheong

IPC: G06F11/10 ,  H03M13/11 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G11C29/52 ,  H03M13/1111 ,  H03M13/3723 ,  H03M13/6325

Abstract: A decoder includes a channel mapper configured to generate a plurality of channel reception values based on hard decision information and soft decision information, a strong error detector configured to determine whether a strong error has occurred using a plurality of check node messages and the channel reception values and to correct the channel reception values according to a determination result to produce corrected channel reception values, a variable node unit configured to generate a plurality of variable node messages using the check node messages and the corrected channel reception values, and a check node unit configured to generate the check node messages using the variable node messages. The variable node unit includes a plurality of variable nodes and the check node unit includes a plurality of check nodes.

公开(公告)号：US20230163786A1

公开(公告)日：2023-05-25

申请号：US17988140

申请日：2022-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Rae KIM ,  Kijun LEE ,  Myungkyu LEE ,  Sunghye CHO ,  Jin-Hoon JANG ,  Isak HWANG

IPC: H03M13/11 ,  H03M13/15 ,  H03M13/09

CPC classification number: H03M13/1174 ,  H03M13/1575 ,  H03M13/098

Abstract: Disclosed is a memory device which includes a memory cell array that stores first data and first parity data, an error correction code (ECC) circuit that performs ECC decoding based on the first data and the first parity data and outputs error-corrected data and a decoding status flag, and an input/output circuit that provides the error-corrected data and the decoding status flag to a memory controller. The ECC circuit includes a syndrome generator that generates a syndrome based on the first data and the first parity data, a syndrome decoding circuit that decodes the syndrome to generate an error vector, a correction logic circuit that generates the error-corrected data based on the error vector and the first data, and a fast decoding status flag (DSF) generator that generates the decoding status flag based on the syndrome, without the error vector.

公开(公告)号：US20230142474A1

公开(公告)日：2023-05-11

申请号：US18093560

申请日：2023-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Rae KIM ,  Myung Kyu LEE ,  Ki Jun LEE ,  Jun Jin KONG ,  Yeong Geol SONG ,  Jin-Hoon JANG

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/00 ,  G11C29/18 ,  G11C29/14

CPC classification number: G11C29/42 ,  G11C29/4401 ,  G11C29/783 ,  G11C29/18 ,  G11C29/14

Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.

公开(公告)号：US20220180958A1

公开(公告)日：2022-06-09

申请号：US17392382

申请日：2021-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Rae KIM ,  Myung Kyu LEE ,  Ki Jun LEE ,  Jun Jin KONG ,  Yeong Geol SONG ,  Jin-Hoon JANG

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/14 ,  G11C29/18 ,  G11C29/00

Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.