公开(公告)号：US20160025484A1

公开(公告)日：2016-01-28

申请号：US14638702

申请日：2015-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Sun KIM ,  Jae-Kyung SEO ,  Kwang-Sub YOON ,  Bi-Zheng WANG ,  Ki-Man LEE ,  Bum-Joon YOUN

IPC: G01B11/27

CPC classification number: G03F7/70633

Abstract: Example embodiments relate to an overlay measurement device and method of forming an overlay pattern. The overlay measurement device includes a tray part with a substrate having a first region and a second region, a measurement part which measures an overlay of a first or second element, and a processor part which receives data measured by the measurement part and corrects the position of the first or second element, wherein the substrate comprises a first layer comprising the first overlay marks, a second layer comprising the second overlay marks, which intersects the first direction, in the second region and not comprising overlay marks which are used to measure the overlay of the second element; and the photoresist pattern which is formed on the first and second layers and overlaps the first and second overlay marks.

Abstract translation: 示例性实施例涉及覆盖测量设备和形成覆盖图案的方法。 覆盖测量装置包括具有第一区域和第二区域的基板的托盘部分，测量第一或第二元件的覆盖层的测量部分和接收由测量部件测量的数据并且校正位置的处理器部件 的第一或第二元件，其中所述基底包括包含所述第一覆盖标记的第一层，在所述第二区域中包括与所述第一方向相交的所述第二覆盖标记的第二层，并且不包括用于测量所述第一覆盖标记的覆盖标记 覆盖第二个元素; 以及形成在第一层和第二层上并与第一和第二覆盖标记重叠的光致抗蚀剂图案。

公开(公告)号：US20130219208A1

公开(公告)日：2013-08-22

申请号：US13747656

申请日：2013-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung-Mook LIM ,  Jin-Su JUNG ,  Kwan-Ho KIM ,  Jung-Rae KIM ,  Tae-Sun KIM

IPC: G06F1/04

CPC classification number: G06F1/04 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076

Abstract: A method of correcting a duty ratio of a data strobe signal is provided. By the method, a duty ratio of a data strobe signal output from a semiconductor memory device is detected and a duty ratio of a clock signal input to the semiconductor memory device is adjusted based on the duty ratio of the data strobe signal.

Abstract translation: 提供了一种校正数据选通信号的占空比的方法。 通过该方法，检测从半导体存储器件输出的数据选通信号的占空比，并且基于数据选通信号的占空比来调整输入到半导体存储器件的时钟信号的占空比。

公开(公告)号：US20150187910A1

公开(公告)日：2015-07-02

申请号：US14505662

申请日：2014-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Sun KIM ,  Jae-Kyung SEO ,  Ji-Ho KIM ,  Kwang-Sub YOON ,  Bum-Joon YOUN ,  Ki-Man LEE

IPC: H01L29/66 ,  H01L21/268 ,  H01L21/266 ,  H01L21/027 ,  H01L21/311

CPC classification number: H01L29/66636 ,  H01L21/0276 ,  H01L21/823418 ,  H01L21/823437 ,  H01L29/165 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7834

Abstract: In a method of manufacturing a semiconductor device, an isolation layer pattern is formed on a substrate to define a field region covered by the isolation layer pattern and first and second active regions that is not covered by the isolation layer pattern and protrudes from the isolation layer pattern. A first anti-reflective layer is formed on the isolation layer pattern. A first photoresist layer is formed on the first and second active regions of the substrate and the first anti-reflective layer. The first photoresist layer is partially etched to form a first photoresist pattern covering the first active region. Impurities are implanted into the second active region to form a first impurity region.

Abstract translation: 在制造半导体器件的方法中，在衬底上形成隔离层图案，以限定由隔离层图案覆盖的场区域和未被隔离层图案覆盖并从隔离层突出的第一和第二有源区域 模式。 第一抗反射层形成在隔离层图案上。 在基板的第一和第二有源区域和第一抗反射层上形成第一光致抗蚀剂层。 部分蚀刻第一光致抗蚀剂层以形成覆盖第一有源区的第一光致抗蚀剂图案。 将杂质注入到第二有源区中以形成第一杂质区。

公开(公告)号：US20140242800A1

公开(公告)日：2014-08-28

申请号：US14190797

申请日：2014-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Hwan OH ,  Yu-Ra KIM ,  Tae-Sun KIM ,  Kwang-Sub YOON

IPC: H01L21/308 ,  H01L21/306

CPC classification number: H01L21/3086 ,  G03F7/091 ,  H01L21/0276 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/32139

Abstract: A method of manufacturing a layer pattern of a semiconductor device, the method including forming an anti-reflective coating (ARC) layer on an etching object layer such that the ARC layer includes a polymer having an imide group; forming a photoresist pattern on the ARC layer; wet etching portions of the ARC layer exposed by the photoresist pattern to form an ARC layer pattern; and etching the etching object layer using the photoresist pattern as an etch mask to form the layer pattern.

Abstract translation: 一种制造半导体器件的层图案的方法，所述方法包括在蚀刻对象层上形成抗反射涂层（ARC）层，使得ARC层包括具有酰亚胺基团的聚合物; 在ARC层上形成光刻胶图案; 通过光致抗蚀剂图案曝光的ARC层的湿蚀刻部分以形成ARC层图案; 并使用光致抗蚀剂图案蚀刻蚀刻对象层作为蚀刻掩模以形成层图案。