公开(公告)号：US20220367416A1

公开(公告)日：2022-11-17

申请号：US17671065

申请日：2022-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkwan Lee ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongwan Kim ,  Hyunki Kim ,  Junwoo Park ,  Hyunggil Baek ,  Junga Lee ,  Taejun Jeon

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor package includes a package substrate having a communication hole extending from an upper surface of the package substrate to a lower surface of the package substrate, a semiconductor chip attached to the upper surface of the package substrate, an auxiliary chip attached to the lower surface of the package substrate, external connection terminals attached to the lower surface of the package substrate and spaced apart from the auxiliary chip, and an encapsulant encapsulating the semiconductor chip and the auxiliary chip and filling the communication hole.

公开(公告)号：US20240128190A1

公开(公告)日：2024-04-18

申请号：US18486546

申请日：2023-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghwan Kim ,  Yongkwan Lee ,  Gyuhyeong Kim ,  Jungjoo Kim ,  Jongwan Kim ,  Junwoo Park ,  Taejun Jeon ,  Junhyeung Jo

IPC: H01L23/528 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5283 ,  H01L21/485 ,  H01L21/56 ,  H01L23/3157 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/05008 ,  H01L2224/13026

Abstract: A semiconductor package includes a lower substrate including a lower interconnection layer; an upper substrate on the lower substrate, a recessed surface having a step difference, and an upper interconnection layer having a through-hole extending from the recessed surface to the first surface of the upper substrate and electrically connected to the lower interconnection layer; semiconductor chip between the recessed surface of the upper substrate and the lower substrate and including connection pads electrically connected to the lower interconnection layer; interconnect structure between the second surface of the upper substrate and the lower substrate and electrically connecting the lower interconnection layer to the upper interconnection layer; and an insulating member including a first portion covering at least a portion of the semiconductor chip and interconnect structure, a second portion extending from the first portion into the through-hole, and a third portion covering at least a portion of the first surface.

公开(公告)号：US12205925B2

公开(公告)日：2025-01-21

申请号：US17671065

申请日：2022-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkwan Lee ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongwan Kim ,  Hyunki Kim ,  Junwoo Park ,  Hyunggil Baek ,  Junga Lee ,  Taejun Jeon

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor package includes a package substrate having a communication hole extending from an upper surface of the package substrate to a lower surface of the package substrate, a semiconductor chip attached to the upper surface of the package substrate, an auxiliary chip attached to the lower surface of the package substrate, external connection terminals attached to the lower surface of the package substrate and spaced apart from the auxiliary chip, and an encapsulant encapsulating the semiconductor chip and the auxiliary chip and filling the communication hole.

公开(公告)号：US20230378094A1

公开(公告)日：2023-11-23

申请号：US18104650

申请日：2023-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junwoo Park ,  Yongkwan Lee ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongwan Kim ,  Taejun Jeon ,  Junhyeung Jo

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H10B80/00

CPC classification number: H01L23/562 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5385 ,  H01L23/49811 ,  H01L23/3128 ,  H10B80/00 ,  H01L2224/16227 ,  H01L24/16 ,  H01L2224/32225 ,  H01L24/32 ,  H01L2224/73204 ,  H01L24/73

Abstract: A semiconductor package includes a support wiring structure, a semiconductor chip on the support wiring structure, a connection structure on the support wiring structure and spaced apart from the semiconductor chip in a horizontal direction, an interposer including a central portion and an outer portion and having a recess portion provided on a lower surface of the central portion facing the semiconductor chip, wherein the central portion is on the semiconductor chip and the connection structure is connected to the outer portion, and a metal plate disposed along a portion of a surface of the recess portion inside the interposer, wherein the metal plate extends along a side surface of the outer portion of the interposer and the lower surface of the central portion of the interposer, and the metal plate has a cavity passing through a vicinity of a center of the metal plate planarly.