公开(公告)号：US09177886B2

公开(公告)日：2015-11-03

申请号：US13672310

申请日：2012-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Han Ko ,  Woo-Dong Lee ,  Tae-Sung Park

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/04 ,  H01L23/12 ,  H01L23/31 ,  H01L25/065 ,  H01L25/10 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/3128 ,  H01L21/563 ,  H01L23/49838 ,  H01L24/73 ,  H01L25/065 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package includes a circuit board comprising a first surface and a second surface opposite the first surface. A first semiconductor chip is stacked on the first surface and a second semiconductor chip stacked on the first semiconductor chip. A region of the second chip protrudes beyond a side of the first semiconductor chip. A support underpins the protruding region of the second chip. The support may be, for example, dry film solder resist dam.

Abstract translation: 半导体封装包括电路板，其包括与第一表面相对的第一表面和第二表面。 第一半导体芯片堆叠在第一表面上，第二半导体芯片堆叠在第一半导体芯片上。 第二芯片的区域突出超过第一半导体芯片的一侧。 支撑件支撑第二芯片的突出区域。 支撑体可以是例如干膜阻焊堤。

公开(公告)号：US20130270717A1

公开(公告)日：2013-10-17

申请号：US13672310

申请日：2012-11-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Han Ko ,  Woo-Dong Lee ,  Tae-Sung Park

IPC: H01L23/48 ,  H01L21/56

CPC classification number: H01L23/3128 ,  H01L21/563 ,  H01L23/49838 ,  H01L24/73 ,  H01L25/065 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package includes a circuit board comprising a first surface and a second surface opposite the first surface. A first semiconductor chip is stacked on the first surface and a second semiconductor chip stacked on the first semiconductor chip. A region of the second chip protrudes beyond a side of the first semiconductor chip. A support underpins the protruding region of the second chip. The support may be, for example, dry film solder resist dam.

Abstract translation: 半导体封装包括电路板，其包括与第一表面相对的第一表面和第二表面。 第一半导体芯片堆叠在第一表面上，第二半导体芯片堆叠在第一半导体芯片上。 第二芯片的区域突出超过第一半导体芯片的一侧。 支撑件支撑第二芯片的突出区域。 支撑体可以是例如干膜阻焊堤。

公开(公告)号：US09257309B2

公开(公告)日：2016-02-09

申请号：US14250360

申请日：2014-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee-Jin Lee ,  Woo-Dong Lee

IPC: H01L21/00 ,  H01L21/50 ,  H01L23/00

CPC classification number: H01L21/50 ,  H01L24/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A multi-chip package may include a package substrate, a first semiconductor chip, a second semiconductor chip and a supporting member. The first semiconductor chip may be arranged on an upper surface of the package substrate. The first semiconductor chip may be electrically connected with the package substrate. The second semiconductor chip may be arranged on an upper surface of the first semiconductor chip. The second semiconductor chip may be electrically connected with the first semiconductor chip. The second semiconductor chip may have a protrusion overhanging an area beyond a side surface of the first semiconductor chip. The supporting member may be interposed between the protrusion of the second semiconductor chip and the package substrate to prevent a deflection of the protrusion. Thus, the protrusion may not be deflected.

Abstract translation: 多芯片封装可以包括封装衬底，第一半导体芯片，第二半导体芯片和支撑构件。 第一半导体芯片可以布置在封装衬底的上表面上。 第一半导体芯片可以与封装衬底电连接。 第二半导体芯片可以布置在第一半导体芯片的上表面上。 第二半导体芯片可以与第一半导体芯片电连接。 第二半导体芯片可以具有突出超过第一半导体芯片的侧表面的区域的突起。 支撑构件可以插入在第二半导体芯片的突起与封装基板之间，以防止突起的偏转。 因此，突起可能不会偏转。