公开(公告)号：US20240145388A1

公开(公告)日：2024-05-02

申请号：US18409447

申请日：2024-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won Kyu HAN ,  Myeongsoo LEE ,  Rakhwan KIM ,  Woojin JANG

IPC: H01L23/528 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L27/092

Abstract: An integrated circuit device includes a substrate and a first electrically insulating layer on the substrate. An electrically conductive contact plug is provided, which extends at least partially through the first electrically insulating layer. The contact plug includes a protrusion having a top surface that is spaced farther from the substrate relative to a top surface of a portion of the first electrically insulating layer extending adjacent the contact plug. An electrically conductive line is provided with a terminal end, which extends on a first portion of the protrusion. A second electrically insulating layer is provided, which extends on a second portion of the protrusion and on the first electrically insulating layer. The second electrically insulating layer has a sidewall, which extends opposite a sidewall of the terminal end of the electrically conductive line.

公开(公告)号：US20220238555A1

公开(公告)日：2022-07-28

申请号：US17722736

申请日：2022-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bio KIM ,  Yujin KIM ,  Philouk NAM ,  Youngseon SON ,  Kyongwon AN ,  Jumi YUN ,  Woojin JANG

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/423 ,  H01L21/02 ,  H01L27/1157 ,  H01L21/28

Abstract: A vertical memory device includes a channel extending in a vertical direction on a substrate, a charge storage structure on an outer sidewall of the channel and including a tunnel insulation pattern, a charge trapping pattern, and a first blocking pattern sequentially stacked in a horizontal direction, and gate electrodes spaced apart from each other in the vertical direction, each of which surrounds the charge storage structure. The charge storage structure includes charge trapping patterns, each of which faces one of the gate electrodes in the horizontal direction. A length in the vertical direction of an inner sidewall of each of the charge trapping patterns facing the tunnel insulation pattern is less than a length in the vertical direction of an outer sidewall thereof facing the first blocking pattern.

公开(公告)号：US20210159174A1

公开(公告)日：2021-05-27

申请号：US16922334

申请日：2020-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungha LEE ,  Woojin JANG

IPC: H01L23/528 ,  H01L23/535 ,  H01L21/768

Abstract: An interconnection structure of an integrated circuit semiconductor device includes: a first conductive layer on a semiconductor substrate; an interlayer insulating layer on the first conductive layer and including a trench and a via hole; a via layer in the via hole, the via layer penetrating the interlayer insulating layer through a bottom of the trench to contact the first conductive layer, the via layer including a protrusion protruding to a height greater than a height of the trench; a barrier layer selectively on the bottom and sidewalls of the trench and on sidewalls of the via layer in the trench; a cap layer on a surface of the via layer; and a second conductive layer in the trench on the barrier layer. The cap layer is electrically connected to the first conductive layer through the via layer.

公开(公告)号：US20220352071A1

公开(公告)日：2022-11-03

申请号：US17856366

申请日：2022-07-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungha LEE ,  Woojin JANG

IPC: H01L23/528 ,  H01L23/535 ,  H01L21/768

Abstract: An interconnection structure of an integrated circuit semiconductor device includes: a first conductive layer on a semiconductor substrate; an interlayer insulating layer on the first conductive layer and including a trench and a via hole; a via layer in the via hole, the via layer penetrating the interlayer insulating layer through a bottom of the trench to contact the first conductive layer, the via layer including a protrusion protruding to a height greater than a height of the trench; a barrier layer selectively on the bottom and sidewalls of the trench and on sidewalls of the via layer in the trench; a cap layer on a surface of the via layer; and a second conductive layer in the trench on the barrier layer. The cap layer is electrically connected to the first conductive layer through the via layer.

公开(公告)号：US20210036012A1

公开(公告)日：2021-02-04

申请号：US16848035

申请日：2020-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bio KIM ,  Yujin KIM ,  Philouk NAM ,  Youngseon SON ,  Kyongwon AN ,  Jumi YUN ,  Woojin JANG

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/423 ,  H01L21/28 ,  H01L27/1157 ,  H01L21/02

Abstract: A vertical memory device includes a channel extending in a vertical direction on a substrate, a charge storage structure on an outer sidewall of the channel and including a tunnel insulation pattern, a charge trapping pattern, and a first blocking pattern sequentially stacked in a horizontal direction, and gate electrodes spaced apart from each other in the vertical direction, each of which surrounds the charge storage structure. The charge storage structure includes charge trapping patterns, each of which faces one of the gate electrodes in the horizontal direction. A length in the vertical direction of an inner sidewall of each of the charge trapping patterns facing the tunnel insulation pattern is less than a length in the vertical direction of an outer sidewall thereof facing the first blocking pattern.

公开(公告)号：US20180114794A1

公开(公告)日：2018-04-26

申请号：US15784635

申请日：2017-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byong-hyun JANG ,  Dongchul YOO ,  Woojin JANG ,  Jaeyoung AHN ,  Junkyu YANG

IPC: H01L27/11582 ,  H01L23/528 ,  H01L29/51 ,  H01L27/11568 ,  H01L21/311 ,  H01L21/762 ,  H01L21/28 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/76224 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/513 ,  H01L29/518

Abstract: A semiconductor device includes word lines vertically stacked on top of each other on a substrate, insulating patterns between the word lines, a vertical pillar connected to the substrate, and residual sacrificial patterns on the substrate at sides of the word lines. The vertical pillar penetrates the word lines and the insulating patterns. Each of the insulating patterns includes a first portion between the word lines and a second portion extending from the first portion and between the residual sacrificial patterns. A first thickness of the first portion is smaller than a second thickness of the second portion.