公开(公告)号：US10276564B2

公开(公告)日：2019-04-30

申请号：US15489093

申请日：2017-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mirco Cantoro ,  Yeon Cheol Heo ,  Byoung Gi Kim ,  Chang Min Yoe ,  Seung Chan Yun ,  Dong Hun Lee ,  Yun Il Lee ,  Hyung Suk Lee

IPC: H01L27/088 ,  H01L29/786 ,  H01L29/06 ,  H01L23/50 ,  H01L21/8234 ,  H01L29/423 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device includes a substrate having a first region and a second region; a first nanowire in the first region in a direction perpendicular to an upper surface of the substrate; a second nanowire in the second region in a direction perpendicular to the upper surface of the substrate and having a height less than that of the first nanowire; first source/drain regions at top portion and bottom portion of the first nanowire; second source/drain regions at top portion and bottom portion of the second nanowire; a first gate electrode surrounding the first nanowire between the first source/drain regions; and a second gate electrode surrounding the second nanowire between the second source/drain regions.

公开(公告)号：US11804490B2

公开(公告)日：2023-10-31

申请号：US17533212

申请日：2021-11-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joong Gun Oh ,  Sung Il Park ,  Jae Hyun Park ,  Hyung Suk Lee ,  Eun Sil Park ,  Yun Il Lee

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/308 ,  H01L29/423 ,  H01L21/768

CPC classification number: H01L27/0924 ,  H01L21/3086 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/0642 ,  H01L29/0847 ,  H01L29/42356 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a fin type pattern extending in a first direction on a substrate, a first gate electrode extending in a second direction intersecting the first direction on the fin type pattern, a source/drain region on a side wall of the first gate electrode and in the fin type pattern, a separation structure extending in the first direction on the substrate, the separation structure including a first trench and being spaced apart from the fin type pattern and separating the first gate electrode, an interlayer insulating layer on a side wall of the separation structure and covering the source/drain region, the interlayer insulating layer including a second trench having a lower surface lower than a lower surface of the first trench, and a contact connected to the source/drain region and filling the first trench and the second trench.

公开(公告)号：US11195833B2

公开(公告)日：2021-12-07

申请号：US16218796

申请日：2018-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joong Gun Oh ,  Sung Il Park ,  Jae Hyun Park ,  Hyung Suk Lee ,  Eun Sil Park ,  Yun Il Lee

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/308 ,  H01L29/423 ,  H01L21/768

Abstract: A semiconductor device includes a fin type pattern extending in a first direction on a substrate, a first gate electrode extending in a second direction intersecting the first direction on the fin type pattern, a source/drain region on a side wall of the first gate electrode and in the fin type pattern, a separation structure extending in the first direction on the substrate, the separation structure including a first trench and being spaced apart from the fin type pattern and separating the first gate electrode, an interlayer insulating layer on a side wall of the separation structure and covering the source/drain region, the interlayer insulating layer including a second trench having a lower surface lower than a lower surface of the first trench, and a contact connected to the source/drain region and filling the first trench and the second trench.

公开(公告)号：US10714599B2

公开(公告)日：2020-07-14

申请号：US16249298

申请日：2019-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun II Lee ,  Sung II Park ,  Jae Hyun Park ,  Hyung Suk Lee

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/02 ,  H01L29/08

Abstract: A semiconductor device including a first fin type pattern and a second fin type pattern which protrude from a substrate and are spaced apart from each other to extend in a first direction, a dummy fin type pattern protruding from the substrate between the first fin type pattern and the second fin type pattern, a first gate structure extending in a second direction intersecting with the first direction, on the first fin type pattern, a second gate structure extending in the second direction, on the second fin type pattern, and a capping pattern extending in the second direction, on the first gate structure and the second gate structure, wherein the capping pattern includes a separation part which is in contact with an upper surface of the dummy fin type pattern, and the dummy fin type pattern and the separation part separate the first gate structure and the second gate structure.

公开(公告)号：US20240055432A1

公开(公告)日：2024-02-15

申请号：US18477290

申请日：2023-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joong Gun Oh ,  Sung Il Park ,  Jae Hyun Park ,  Hyung Suk Lee ,  Eun Sil Park ,  Yun Il Lee

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/308 ,  H01L29/423 ,  H01L21/768

CPC classification number: H01L27/0924 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/0642 ,  H01L29/6656 ,  H01L29/0847 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823871 ,  H01L21/3086 ,  H01L29/42356 ,  H01L21/76895

Abstract: A semiconductor device includes a fin type pattern extending in a first direction on a substrate, a first gate electrode extending in a second direction intersecting the first direction on the fin type pattern, a source/drain region on a side wall of the first gate electrode and in the fin type pattern, a separation structure extending in the first direction on the substrate, the separation structure including a first trench and being spaced apart from the fin type pattern and separating the first gate electrode, an interlayer insulating layer on a side wall of the separation structure and covering the source/drain region, the interlayer insulating layer including a second trench having a lower surface lower than a lower surface of the first trench, and a contact connected to the source/drain region and filling the first trench and the second trench.

公开(公告)号：US12279458B2

公开(公告)日：2025-04-15

申请号：US18477290

申请日：2023-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joong Gun Oh ,  Sung Il Park ,  Jae Hyun Park ,  Hyung Suk Lee ,  Eun Sil Park ,  Yun Il Lee

IPC: H01L27/092 ,  H01L21/308 ,  H01L21/768 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H10D30/01 ,  H10D30/62 ,  H10D62/10 ,  H10D62/13 ,  H10D64/01 ,  H10D64/27 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85 ,  H01L21/8238

Abstract: A semiconductor device includes a fin type pattern extending in a first direction on a substrate, a first gate electrode extending in a second direction intersecting the first direction on the fin type pattern, a source/drain region on a side wall of the first gate electrode and in the fin type pattern, a separation structure extending in the first direction on the substrate, the separation structure including a first trench and being spaced apart from the fin type pattern and separating the first gate electrode, an interlayer insulating layer on a side wall of the separation structure and covering the source/drain region, the interlayer insulating layer including a second trench having a lower surface lower than a lower surface of the first trench, and a contact connected to the source/drain region and filling the first trench and the second trench.

公开(公告)号：US10249757B2

公开(公告)日：2019-04-02

申请号：US15386901

申请日：2016-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bong Cheol Kim ,  Hyung Suk Lee ,  Eun Shoo Han

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/165 ,  H01L29/10

Abstract: A substrate includes a pattern forming region and a peripheral region. A first strain relaxed buffer layer is disposed on the pattern forming region of the substrate. A second strain relaxed buffer layer is disposed on the peripheral region of the substrate. A first insulating film pattern is disposed on the substrate. At least a portion of the first insulating film pattern is disposed within the first strain relaxed buffer layer. An upper surface of the first insulating film pattern is covered with the first strain relaxed buffer layer. A second insulating film pattern is disposed on the substrate. At least a portion of the second insulating film pattern is disposed within the second strain relaxed buffer layer. An upper surface of the second insulating film pattern is covered with the second strain relaxed buffer layer. A gate electrode is disposed on the first strain relaxed buffer layer.

公开(公告)号：US09786784B1

公开(公告)日：2017-10-10

申请号：US15271660

申请日：2016-09-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Seung Song ,  Soo Yeon Jeong ,  Hyung Suk Lee

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L21/306 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/30604 ,  H01L29/41791 ,  H01L29/4236 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827

Abstract: A vertical fin field effect transistor (V-FinFET) is provided as follows. A T-shaped fin structure extend vertically from an upper surface of a substrate. The T-shaped fin structure includes a lower part and an upper part. The lower part is in contact with the upper surface of the substrate. The upper part of the T-shaped fin structure is vertically stacked on the lower part of the T-shaped fin structure. A gate insulating layer surrounds the lower part. A work-function-control pattern surrounds the lower part. The gate insulating layer is interposed between the work-function-control pattern and the lower part of the T-shaped fin structure. A gate electrode is disposed on a sidewall of the work-function-control pattern.