公开(公告)号：US10692858B2

公开(公告)日：2020-06-23

申请号：US16393504

申请日：2019-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： YeonCheol Heo

IPC: H01L27/06 ,  H01L21/8234 ,  H01L21/8249 ,  H01L29/06 ,  H01L27/12 ,  H01L29/66 ,  H01L29/732 ,  H01L29/08 ,  H01L29/10 ,  H01L29/786 ,  H01L29/423 ,  H01L29/737

Abstract: A semiconductor device may include a substrate, a first doped region and a second doped region on the substrate, a base region on the first doped region, a channel region on the second doped region, and a third doped region and a fourth doped region on the base region and the channel region, respectively. The first doped region and the second doped region may be isolated from direct contact with each other in a first direction that is substantially parallel to a top surface of the substrate. A channel gate structure may be on a side surface of the channel region. A thickness of the base region, in a second direction that is substantially perpendicular to the top surface of the substrate, may be equal to or larger than a thickness of the channel region.

公开(公告)号：US10319715B2

公开(公告)日：2019-06-11

申请号：US15627768

申请日：2017-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： YeonCheol Heo

IPC: H01L21/8249 ,  H01L29/06 ,  H01L27/06 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/737

Abstract: A semiconductor device may include a substrate, a first doped region and a second doped region on the substrate, a base region on the first doped region, a channel region on the second doped region, and a third doped region and a fourth doped region on the base region and the channel region, respectively. The first doped region and the second doped region may be isolated from direct contact with each other in a first direction that is substantially parallel to a top surface of the substrate. A channel gate structure may be on a side surface of the channel region. A thickness of the base region, in a second direction that is substantially perpendicular to the top surface of the substrate, may be equal to or larger than a thickness of the channel region.

公开(公告)号：US09966377B2

公开(公告)日：2018-05-08

申请号：US15409202

申请日：2017-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mirco Cantoro ,  YeonCheol Heo

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8258 ,  H01L21/306 ,  H01L29/267 ,  H01L29/06 ,  H01L27/11 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/8258 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0649 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate with an NMOSFET region and a PMOSFET region, a first active pattern on the NMOSFET region, a second active pattern on the PMOSFET region, a dummy pattern between the NMOSFET and PMOSFET regions, and device isolation patterns on the substrate that fill trenches between the first active pattern, the second active pattern, and the dummy pattern. Upper portions of the first and second active patterns have a fin-shaped structure protruding between the device isolation patterns. The upper portions of the first and second active patterns contain semiconductor materials, respectively, that are different from each other, and an upper portion of the dummy pattern contains an insulating material.

公开(公告)号：US20190252371A1

公开(公告)日：2019-08-15

申请号：US16393504

申请日：2019-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： YeonCheol Heo

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L21/8249 ,  H01L29/66 ,  H01L27/12 ,  H01L21/8234 ,  H01L29/732

Abstract: A semiconductor device may include a substrate, a first doped region and a second doped region on the substrate, a base region on the first doped region, a channel region on the second doped region, and a third doped region and a fourth doped region on the base region and the channel region, respectively. The first doped region and the second doped region may be isolated from direct contact with each other in a first direction that is substantially parallel to a top surface of the substrate. A channel gate structure may be on a side surface of the channel region. A thickness of the base region, in a second direction that is substantially perpendicular to the top surface of the substrate, may be equal to or larger than a thickness of the channel region.

公开(公告)号：US10211339B2

公开(公告)日：2019-02-19

申请号：US15397011

申请日：2017-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： YeonCheol Heo ,  Mirco Cantoro

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423

Abstract: A semiconductor device includes a semiconductor substrate including a first source/drain region formed in an upper portion of the semiconductor substrate, a metal silicide layer that covers a top surface of the first source/drain region, and a semiconductor pillar that penetrates the metal silicide layer and is connected to the semiconductor substrate. The semiconductor pillar includes a second source/drain region formed in an upper portion of the semiconductor pillar, a gate electrode on the metal silicide layer, with the gate electrode surrounding the semiconductor pillar in a plan view. A contact is connected to the metal silicide layer.

公开(公告)号：US20170271508A1

公开(公告)日：2017-09-21

申请号：US15397011

申请日：2017-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： YeonCheol Heo ,  Mirco Cantoro

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7827 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/66666

Abstract: A semiconductor device includes a semiconductor substrate including a first source/drain region formed in an upper portion of the semiconductor substrate, a metal silicide layer that covers a top surface of the first source/drain region, and a semiconductor pillar that penetrates the metal silicide layer and is connected to the semiconductor substrate. The semiconductor pillar includes a second source/drain region formed in an upper portion of the semiconductor pillar, a gate electrode on the metal silicide layer, with the gate electrode surrounding the semiconductor pillar in a plan view. A contact is connected to the metal silicide layer.