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    SEMICONDUCTOR PACKAGE
    1.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220013498A1

    公开(公告)日：2022-01-13

    申请号：US17196470

    申请日：2021-03-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yong Ho KIM

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538

    Abstract: A semiconductor package includes a redistribution layer including, a first insulating layer including a first trench, a first conductive layer including a first conductive region extending along a top surface of the first insulating layer and a second conductive region disposed inside the first trench, a second insulating layer on the first conductive layer and the first insulating layer, the second insulating layer including a second trench at least partially overlapping the first trench, the second trench exposing a part of the first conductive region and a second conductive layer including a third conductive region extending along a top surface of the second insulating layer and a fourth conductive region disposed on the second conductive region inside a via trench including sidewalls of the first trench and the second trench, and wherein the second and fourth conductive regions have a width in a range of 20 μm to 600 μm.

    SEMICONDUCTOR PACKAGE
    3.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230034654A1

    公开(公告)日：2023-02-02

    申请号：US17702259

    申请日：2022-03-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yong Ho KIM ,  Bo In NOH ,  Jeong Hoon AHN

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/10

    Abstract: A semiconductor package is provided. The semiconductor package includes: a first stack including a first semiconductor substrate; a through via that penetrates the first semiconductor substrate in a first direction; a second stack that includes a second face facing a first face of the first stack, on the first stack; a first pad that is in contact with the through via, on the first face of the first stack; a second pad including a concave inner side face that defines an insertion recess, the second pad located on the second face of the second stack; and a bump that connects the first pad and the second pad, wherein the bump includes a first upper bump on the first pad, and a first lower bump between the first upper bump and the first pad.

    ELECTRONIC APPARATUS AND METHOD FOR OPERATING SAME
    4.
    发明申请
    ELECTRONIC APPARATUS AND METHOD FOR OPERATING SAME 审中-公开

    公开(公告)号：US20200051554A1

    公开(公告)日：2020-02-13

    申请号：US16478719

    申请日：2017-12-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yong Ho KIM ,  Sourabh PATERIYA ,  Sunah KIM ,  Gahyun JOO ,  Sang-Woong HWANG ,  Say JANG

    IPC: G10L15/22 ,  G06F3/16

    Abstract: Various embodiments of the disclosure disclose a method and apparatus for processing a voice recognition service in an electronic device. According to various embodiments of the disclosure, an electronic device may include a microphone, a memory, and a processor operatively coupled to the microphone and the memory. The processor may be configured to wake-up on the basis of detection of a wake-up word, process a first task corresponding to a first voice command of a user on the basis of the wake-up, set a wait time during which a follow-up command can be received on the basis of the processing of the first task, detect a second voice command of the user during the wait time, analyze a conversational context on the basis of the first voice command and second voice command, and process a second task on the basis of a result of the analysis. Various embodiments are possible.

    SEMICONDUCTOR PACKAGE
    5.
    发明公开
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20230197683A1

    公开(公告)日：2023-06-22

    申请号：US18169713

    申请日：2023-02-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yong Ho KIM

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538

    CPC classification number: H01L25/0655 ,  H01L24/16 ,  H01L24/06 ,  H01L23/5383 ,  H01L23/5384 ,  H01L2224/0401 ,  H01L2224/16227

    Abstract: A semiconductor package includes a redistribution layer including, a first insulating layer including a first trench, a first conductive layer including a first conductive region extending along a top surface of the first insulating layer and a second conductive region disposed inside the first trench, a second insulating layer on the first conductive layer and the first insulating layer, the second insulating layer including a second trench at least partially overlapping the first trench, the second trench exposing a part of the first conductive region and a second conductive layer including a third conductive region extending along a top surface of the second insulating layer and a fourth conductive region disposed on the second conductive region inside a via trench including sidewalls of the first trench and the second trench, and wherein the second and fourth conductive regions have a width in a range of 20 μm to 600 μm.

    SEMICONDUCTOR PACKAGE
    8.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230099844A1

    公开(公告)日：2023-03-30

    申请号：US17830488

    申请日：2022-06-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yong Ho KIM ,  Woo Jin JANG ,  Jeong Hoon AHN ,  Yun Ki CHOI

    IPC: H01L23/00 ,  H01L25/065

    Abstract: Provided is a semiconductor package including a first chip substrate including a first surface and a second surface, a through via passing through the first chip substrate, an upper passivation layer including a trench on the second surface of the first chip substrate, the trench exposing at least a portion of the second surface of the first chip substrate, an upper pad electrically connected with the through via on the trench, a second chip substrate including a third surface and a fourth surface, a lower pad electrically connected to the second chip substrate on the third surface of the second chip substrate, and a connection bump electrically connecting the upper pad with the lower pad and contacting the lower pad, wherein a width of the connection bump increases as the connection bump becomes farther away from the first surface of the first chip substrate.

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