公开(公告)号：US20240021704A1

公开(公告)日：2024-01-18

申请号：US18176170

申请日：2023-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangmoon LEE ,  Jinbum KIM ,  Dongwoo KIM ,  Hyojin KIM ,  Yongjun NAM ,  Ingeon HWANG

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/775 ,  H01L29/423 ,  H01L27/092

CPC classification number: H01L29/66545 ,  H01L29/78696 ,  H01L29/0673 ,  H01L21/823807 ,  H01L29/775 ,  H01L29/66439 ,  H01L29/42392 ,  H01L29/78687 ,  H01L27/092

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern including a plurality of semiconductor patterns spaced apart from each other and vertically stacked, on the active pattern, a source/drain pattern connected to the plurality of semiconductor patterns, and a gate electrode including a first inner electrode provided below a first semiconductor pattern among the plurality of semiconductor patterns, on the plurality of semiconductor patterns, and a second inner electrode provided above the first semiconductor pattern, the first semiconductor pattern includes a first portion adjacent to the first inner electrode, a second portion adjacent to the second inner electrode, and a third portion between the first and second portions, the first semiconductor pattern includes a dopant having an atomic weight greater than that of silicon, and a dopant concentration of the third portion is smaller than a dopant concentration of each of the first and second portions.

公开(公告)号：US20230411487A1

公开(公告)日：2023-12-21

申请号：US18112122

申请日：2023-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjun NAM ,  Sangmoon LEE ,  Jinbum KIM ,  Hyojin KIM

IPC: H01L29/49 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/4908 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/775

Abstract: A semiconductor device may include a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns, which are vertically stacked to be spaced apart from each other, a source/drain pattern connected to the plurality of semiconductor patterns, a gate electrode including a plurality of gate electrode portions, a gate electrode portion interposed between adjacent ones of the semiconductor patterns, and a plurality of barrier patterns each comprising an epitaxial layer including single-crystalline silicon oxide. ,A barrier pattern interposed between each of the adjacent ones of the semiconductor patterns and a respective gate electrode portion.

公开(公告)号：US20230006040A1

公开(公告)日：2023-01-05

申请号：US17577088

申请日：2022-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangmoon LEE ,  Jinbum KIM ,  Hyojin KIM ,  Yongjun NAM ,  Sujin JUNG

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/423

Abstract: An integrated circuit (IC) device includes a fin-type active region extending on a substrate in a first lateral direction. A gate line extends on the fin-type active region in a second lateral direction. The second lateral direction intersects the first lateral direction. A channel region is between the substrate and the gate line. A source/drain region is adjacent to the gate line on the fin-type active region and has a sidewall facing the channel region. A superlattice barrier is between the substrate and the channel region. The superlattice barrier is in contact with the source/drain region. The superlattice barrier has a structure in which a plurality of first sub-layers including a semiconductor layer doped with oxygen atoms and a plurality of second sub-layers including an undoped semiconductor layer are alternately stacked.