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    Three-dimensional resistive random access memory devices, methods of operating the same, and methods of fabricating the same
    1.
    发明授权
    Three-dimensional resistive random access memory devices, methods of operating the same, and methods of fabricating the same 有权
    三维电阻随机存取存储器件，其操作方法及其制造方法

    公开(公告)号：US09093369B2

    公开(公告)日：2015-07-28

    申请号：US13783663

    申请日：2013-03-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yoocheol Shin ,  Min Kyu Yang

    IPC: H01L29/02 ,  H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2436 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

    Abstract: A semiconductor device includes a substrate extending in a horizontal direction. An active pillar is present on the substrate extending in a vertical direction relative to the horizontal direction of extension of the substrate. A variable resistive pattern is present on the substrate extending in the vertical direction along the active pillar, an electrical resistance of the variable resistive pattern being variable in response to an oxidation or reduction thereof. A gate is present at a sidewall of the active pillar.

    Abstract translation: 半导体器件包括沿水平方向延伸的衬底。 有源柱存在于基板上，相对于基板的延伸水平方向在垂直方向上延伸。 可变电阻图案存在于沿着有源柱沿垂直方向延伸的衬底上，可变电阻图案的电阻响应于氧化或还原而变化。 门处于活动柱的侧壁处。

    Three-dimensional semiconductor memory device
    3.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US10032787B2

    公开(公告)日：2018-07-24

    申请号：US15652411

    申请日：2017-07-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yoocheol Shin ,  Hongsoo Kim ,  Jaesung Sim

    IPC: H01L27/115 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11548 ,  G11C16/04 ,  H01L27/11582 ,  H01L27/11531 ,  H01L27/105

    Abstract: A three-dimensional semiconductor memory device includes stacked structures, vertical semiconductor patterns, common source regions, and well pickup regions. The stacked structures are disposed on a semiconductor layer of a first conductivity type. Each stacked structure includes electrodes vertically stacked on each other and is extended in a first direction. The vertical semiconductor patterns penetrate the stacked structures. The common source regions of a second conductivity type are disposed in the semiconductor layer. At least one common source region is disposed between two adjacent stacked structures. The at least one common source region is extended in the first direction. The well pickup regions of the first conductivity type are disposed in the semiconductor layer. At least one well pickup region is adjacent to both ends of at least one stacked structure.

    Nonvolatile memory device
    4.
    发明授权
    Nonvolatile memory device 有权
    非易失性存储器件

    公开(公告)号：US08923058B2

    公开(公告)日：2014-12-30

    申请号：US13653798

    申请日：2012-10-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changyun Lee ,  Yoocheol Shin ,  Jungdal Choi

    IPC: G11C16/04 ,  G11C5/06 ,  G11C5/02 ,  G11C5/04 ,  G11C11/34

    CPC classification number: G11C11/34 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418

    Abstract: A nonvolatile memory device is provided. The device may include a plurality of cell strings that are configured to share a bit line, word lines, and selection lines. Each of the cell strings may include a plurality of memory cells connected in series to each other and a string selection device controlling connections between the memory cells and the bit line, and the string selection device may include a first string selection element with a first threshold voltage and a second string selection element connected in series to the first string selection element and having a second threshold voltage different from the first threshold voltage. At least one of the first and second string selection elements may include a plurality of switching elements connected in series to each other.

    Abstract translation: 提供非易失性存储器件。 该设备可以包括被配置为共享位线，字线和选择线的多个单元串。 每个单元串可以包括彼此串联连接的多个存储器单元和用于控制存储器单元和位线之间的连接的串选择装置，并且串选择装置可以包括具有第一阈值的第一串选择元件 电压和第二串选择元件串联连接到第一串选择元件并且具有不同于第一阈值电压的第二阈值电压。 第一和第二串选择元件中的至少一个可以包括彼此串联连接的多个开关元件。

    Semiconductor device and method of fabricating the same
    6.
    发明授权
    Semiconductor device and method of fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US09472568B2

    公开(公告)日：2016-10-18

    申请号：US14502115

    申请日：2014-09-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yoocheol Shin ,  Jaegoo Lee ,  Young-Jin Kwon ,  Jintaek Park

    IPC: H01L27/115 ,  H01L21/768

    CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L27/1157 ,  H01L27/11575

    Abstract: A semiconductor device is provided as follows. A peripheral circuit structure is disposed on a first substrate. A cell array structure is disposed on the peripheral circuit structure. A second substrate is interposed between the peripheral circuit structure and the cell array structure. The cell array structure includes a stacked structure, a through hole and a vertical semiconductor pattern. The stacked structure includes gate electrodes stacked on the second substrate. The through hole penetrates the stacked structure and the second substrate to expose the peripheral circuit structure. The vertical semiconductor pattern is disposed on the peripheral circuit structure, filling the through hole.

    Abstract translation: 如下提供半导体器件。 外围电路结构设置在第一基板上。 电池阵列结构设置在外围电路结构上。 第二基板介于外围电路结构和电池阵列结构之间。 电池阵列结构包括堆叠结构，通孔和垂直半导体图案。 层叠结构包括层叠在第二基板上的栅电极。 通孔贯穿堆叠结构和第二基板，露出外围电路结构。 垂直半导体图案设置在外围电路结构上，填充通孔。

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