公开(公告)号：US20230240073A1

公开(公告)日：2023-07-27

申请号：US18063878

申请日：2022-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonhwan SON ,  Miso KIM ,  Joongshik SHIN ,  Minjae OH

IPC: H10B43/27 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B41/50 ,  H10B43/50 ,  H01L21/28

CPC classification number: H10B43/27 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B41/50 ,  H10B43/50 ,  H01L29/40117

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first stack structure in the first region, a first channel structure penetrating through the first stack structure and in contact with the substrate, and a second stack structure on the first stack structure and the first channel structure. The device includes a second channel structure penetrating through the second stack structure and connected to the first channel structure, a first molding structure in the second region, a first alignment structure penetrating through the first molding structure and in contact with the substrate, and a second molding structure on the first molding structure and the first alignment structure. The device includes a second alignment structure penetrating through the second molding structure and connected to the first alignment structure, and a protective layer between the first molding structure and the second molding structure.

公开(公告)号：US20210028186A1

公开(公告)日：2021-01-28

申请号：US15930867

申请日：2020-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geunwon LIM ,  Yoonhwan SON ,  Junyoung CHOI

IPC: H01L27/11582 ,  H01L29/51 ,  H01L27/11565 ,  H01L21/28

Abstract: Vertical memory devices and method of manufacturing the same are disclosed. The vertical memory device includes a substrate having a cell block area, a block separation area and a boundary area, a plurality of stack structures arranged in the cell block area and the boundary area such that insulation interlayer patterns are stacked on the substrate alternately with the electrode patterns. The stack structures are spaced apart by the block separation area in the third direction. A plurality of channel structures extend through the stack structures to the substrate in the cell block area in the first direction and are connected to the substrate. A plurality of dummy channel structures extend through upper portions of each of the stack structures in the boundary area and are connected to a dummy bottom electrode pattern spaced apart from the substrate. The bridge defect is thus substantially prevented near the substrate.

公开(公告)号：US20230025248A1

公开(公告)日：2023-01-26

申请号：US17861573

申请日：2022-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonhwan SON ,  Minsoo SHIN ,  Joongshik SHIN

IPC: H01L27/11582 ,  H01L27/11573 ,  G11C16/04

Abstract: A three-dimensional semiconductor memory device may include a substrate, a stack structure including interlayer dielectric layers and gate electrodes alternately and repeatedly stacked on the substrate and including a first stack structure on the substrate and a second stack structure on the first stack structure, a seed layer interposed between the first and second stack structures and extended in a horizontal direction, vertical channel structures that penetrate the stack structure and are in contact with the substrate, and a first contact plug that penetrates the stack structure and is in contact with one of the gate electrodes. The seed layer may include first and second seed patterns enclosing the vertical channel structures and the first contact plug, and the first and second seed patterns may be spaced apart from each other in the horizontal direction.

公开(公告)号：US20220020762A1

公开(公告)日：2022-01-20

申请号：US17236053

申请日：2021-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonhwan SON ,  Gaeun KIM ,  Jeongseok LEE

IPC: H01L27/11573 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582

Abstract: A three-dimensional semiconductor memory device includes a peripheral circuit structure having peripheral circuits on a semiconductor substrate, and landing pads connected to the peripheral circuits, an electrode structure on the peripheral circuit structure, the electrode structure including vertically stacked electrodes, a planarized dielectric layer that covers the electrode structure, peripheral through plugs spaced apart from the electrode structure, the peripheral through plugs penetrating the planarized dielectric layer to connect to the landing pads, conductive lines connected through contact plugs, respectively, to the peripheral through plugs, and at least one dummy through plug adjacent to a first peripheral through plug of the peripheral through plugs, the at least one dummy through plug penetrating the planarized dielectric layer and being insulated from the conductive lines.