公开(公告)号：US20190109135A1

公开(公告)日：2019-04-11

申请号：US16203946

申请日：2018-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Jung KIM ,  Young Suk CHAI ,  Sang Yong KIM ,  Hoon Joo NA ,  Sang Jin HYUN

IPC: H01L27/092 ,  B82Y10/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L29/40 ,  H01L29/10 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/775

Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.

公开(公告)号：US20170256544A1

公开(公告)日：2017-09-07

申请号：US15351673

申请日：2016-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Suk CHAI ,  Hu Yong LEE ,  Sang Yong KIM ,  Taek Soo JEON ,  Won Keun CHUNG ,  Sang Jin HYUN

IPC: H01L27/092 ,  H01L29/423 ,  H01L21/306 ,  H01L21/311 ,  H01L29/51 ,  H01L21/8234

CPC classification number: H01L27/0922 ,  B82Y10/00 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device including a MOS transistor is provided. The semiconductor device may include a first MOS transistor including first source/drain regions, a first semiconductor layer between the first source/drain regions, a first gate electrode structure, and a first gate dielectric structure; and a second MOS transistor including second source/drain regions, a second semiconductor layer between the second source/drain regions, a second gate electrode structure, and a second gate dielectric structure. The first gate dielectric structure and the second gate dielectric structure include a first common dielectric structure; the first gate dielectric structure includes a first upper dielectric on the first common dielectric structure; the second gate dielectric structure includes the first upper dielectric and a second upper dielectric; and one of the first upper dielectric and the second upper dielectric is a material forming a dipole layer.

公开(公告)号：US20210013207A1

公开(公告)日：2021-01-14

申请号：US17038964

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Jung KIM ,  Young Suk CHAI ,  Sang Yong KIM ,  Hoon Joo NA ,  Sang Jin HYUN

IPC: H01L27/092 ,  H01L29/423 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/775 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78

Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.

公开(公告)号：US20180069006A1

公开(公告)日：2018-03-08

申请号：US15452203

申请日：2017-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Jung Kim ,  Young Suk CHAI ,  Sang Yong KIM ,  Hoon Joo NA ,  Sang Jin HYUN

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/02

CPC classification number: H01L27/0924 ,  B82Y10/00 ,  H01L21/02603 ,  H01L21/823821 ,  H01L21/823842 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7845

Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.