公开(公告)号：US20200219808A1

公开(公告)日：2020-07-09

申请号：US16441042

申请日：2019-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soon Gyu HWANG ,  Kyoung Woo LEE ,  YoungWoo CHO ,  IL SUP KIM ,  Su Hyun BARK ,  Young-Ju PARK ,  Jong Min BAEK ,  Min HUH

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device includes a substrate, a first lower wiring line on the substrate, a first insulation layer on the first lower wiring line, a first dielectric barrier layer and a first etch stop layer sequentially stacked on the first insulation layer, a second insulation layer on the first etch stop layer, a first upper wiring line extending through the second insulation layer, the first etch stop layer, and the first dielectric barrier layer, and a first conductive via in the first insulation layer and electrically connecting the first lower wiring line and the first upper wiring line. An upper surface of the first conductive via protrudes above a lower surface of the first upper wiring line.

公开(公告)号：US20150137261A1

公开(公告)日：2015-05-21

申请号：US14602716

申请日：2015-01-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Wook LEE ,  Myeong-Cheol KIM ,  Sang-Min LEE ,  Young-Ju PARK ,  Hyung-Yong KIM ,  Myung-Hoon JUNG

IPC: H01L29/78 ,  H01L27/11

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/11 ,  H01L29/66636 ,  H01L29/78

Abstract: A fabricating method of a semiconductor device includes providing a substrate having a first region and a second region, forming a plurality of first gates in the first region of the substrate, such that the first gates are spaced apart from each other at a first pitch, forming a plurality of second gates in the second region of the substrate, such that the second gates are spaced apart from each other at a second pitch different from the first pitch, implanting an etch rate adjusting dopant into the second region to form implanted regions, while blocking the first region, forming a first trench by etching the first region between the plurality of first gates, and forming a second trench by etching the second region between the plurality of second gates.

Abstract translation: 半导体器件的制造方法包括提供具有第一区域和第二区域的衬底，在衬底的第一区域中形成多个第一栅极，使得第一栅极以第一间距相互间隔开， 在所述衬底的所述第二区域中形成多个第二栅极，使得所述第二栅极以不同于所述第一间距的第二间距彼此间隔开，将蚀刻速率调节掺杂剂注入所述第二区域以形成注入区域， 同时阻挡第一区域，通过蚀刻多个第一栅极之间的第一区域形成第一沟槽，并且通过蚀刻多个第二栅极之间的第二区域形成第二沟槽。

公开(公告)号：US20140057427A1

公开(公告)日：2014-02-27

申请号：US14070935

申请日：2013-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Kwon KIM ,  Young-Ju PARK ,  Dong-Hyuk YEAM ,  Yoo-jung LEE ,  Myeong-cheol KIM ,  Do-Hyoung KIM ,  Heung-Sik PARK

IPC: H01L21/28

CPC classification number: H01L21/28132 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656

Abstract: Example embodiments relate to a method for manufacturing a semiconductor device, wherein a metal gate electrode therein may be formed without a void in a lower portion of the metal gate electrode. The method may include providing a substrate, forming a dummy gate electrode on the substrate, forming a gate spacer on the substrate to be contiguous to the dummy gate electrode, forming a first recess by simultaneously removing a portion of the dummy gate electrode and a portion of the gate spacer, the first recess having an upper end wider than a lower end, forming a second recess by removing the dummy gate electrode remaining after forming the first recess, and forming a metal gate electrode by depositing a metal to fill the first and second recesses.

Abstract translation: 示例性实施例涉及用于制造半导体器件的方法，其中可以在金属栅电极的下部中形成其中的金属栅极电极，而不产生空隙。 该方法可以包括提供衬底，在衬底上形成虚拟栅电极，在衬底上形成与虚拟栅电极相邻的栅极间隔物，通过同时去除虚拟栅电极的一部分形成第一凹槽， 所述第一凹部具有比下端更宽的上端，通过去除在形成所述第一凹部之后残留的所述虚设栅电极形成第二凹槽，以及通过沉积金属以填充所述第一凹部而形成金属栅电极，以填充所述第一凹部 第二个凹槽

公开(公告)号：US20140110757A1

公开(公告)日：2014-04-24

申请号：US14138721

申请日：2013-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Wook LEE ,  Myeong-Cheol KIM ,  Sang-Min LEE ,  Young-Ju PARK ,  Hyung-Yong KIM ,  Myung-Hoon JUNG

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/265

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/11 ,  H01L29/66636 ,  H01L29/78

Abstract: A fabricating method of a semiconductor device includes providing a substrate having a first region and a second region, forming a plurality of first gates in the first region of the substrate, such that the first gates are spaced apart from each other at a first pitch, forming a plurality of second gates in the second region of the substrate, such that the second gates are spaced apart from each other at a second pitch different from the first pitch, implanting an etch rate adjusting dopant into the second region to form implanted regions, while blocking the first region, forming a first trench by etching the first region between the plurality of first gates, and forming a second trench by etching the second region between the plurality of second gates.

Abstract translation: 半导体器件的制造方法包括提供具有第一区域和第二区域的衬底，在衬底的第一区域中形成多个第一栅极，使得第一栅极以第一间距相互间隔开， 在所述衬底的所述第二区域中形成多个第二栅极，使得所述第二栅极以不同于所述第一间距的第二间距彼此间隔开，将蚀刻速率调节掺杂剂注入所述第二区域以形成注入区域， 同时阻挡第一区域，通过蚀刻多个第一栅极之间的第一区域形成第一沟槽，并且通过蚀刻多个第二栅极之间的第二区域形成第二沟槽。