公开(公告)号：US11991879B2

公开(公告)日：2024-05-21

申请号：US17155441

申请日：2021-01-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoo-cheol Shin ,  Young-woo Park ,  Jae-duk Lee

IPC: H01L27/11578 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H10B41/20 ,  H10B41/27 ,  H10B41/40 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/20 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H10B41/20 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.

公开(公告)号：US10381370B2

公开(公告)日：2019-08-13

申请号：US15869888

申请日：2018-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoo-cheol Shin ,  Young-woo Park ,  Jae-duk Lee

IPC: H01L51/00 ,  H01L27/11578 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L27/1157

Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.

公开(公告)号：US09355969B2

公开(公告)日：2016-05-31

申请号：US14723721

申请日：2015-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-woo Park

IPC: H01L23/552 ,  H01L23/58 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065

CPC classification number: H01L23/58 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/5384 ,  H01L23/552 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor package includes a package substrate including a ground pad; a a conductive spacer and a first semiconductor chip disposed on the package substrate; a second semiconductor chip on the conductive spacer and the first semiconductor chip; a molding unit that covers the package substrate, the first semiconductor chip, the second semiconductor chip, and a first portion of the conductive spacer, and exposes a second portion of the conductive spacer; and an electromagnetic interference (EMI) shield that covers the molding unit.

Abstract translation: 半导体封装包括包括接地焊盘的封装基板; 导电间隔物和设置在封装基板上的第一半导体芯片; 导电间隔物和第一半导体芯片上的第二半导体芯片; 覆盖所述封装基板，所述第一半导体芯片，所述第二半导体芯片和所述导电间隔物的第一部分的模制单元，并且暴露所述导电间隔物的第二部分; 以及覆盖模制单元的电磁干扰（EMI）屏蔽。

公开(公告)号：US20160071810A1

公开(公告)日：2016-03-10

申请号：US14723721

申请日：2015-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-woo Park

IPC: H01L23/58 ,  H01L23/528 ,  H01L25/065 ,  H01L23/522

CPC classification number: H01L23/58 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/5384 ,  H01L23/552 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor package includes a package substrate including a ground pad; a a conductive spacer and a first semiconductor chip disposed on the package substrate; a second semiconductor chip on the conductive spacer and the first semiconductor chip; a molding unit that covers the package substrate, the first semiconductor chip, the second semiconductor chip, and a first portion of the conductive spacer, and exposes a second portion of the conductive spacer; and an electromagnetic interference (EMI) shield that covers the molding unit.

Abstract translation: 半导体封装包括包括接地焊盘的封装基板; 导电间隔物和设置在封装基板上的第一半导体芯片; 导电间隔物和第一半导体芯片上的第二半导体芯片; 覆盖所述封装基板，所述第一半导体芯片，所述第二半导体芯片和所述导电间隔物的第一部分的模制单元，并且暴露所述导电间隔物的第二部分; 以及覆盖模制单元的电磁干扰（EMI）屏蔽。

公开(公告)号：US10903226B2

公开(公告)日：2021-01-26

申请号：US16844064

申请日：2020-04-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoo-cheol Shin ,  Young-woo Park ,  Jae-duk Lee

IPC: H01L27/11578 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11582 ,  H01L27/1157

Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.

公开(公告)号：US20190252401A1

公开(公告)日：2019-08-15

申请号：US16396027

申请日：2019-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoo-cheol Shin ,  Young-woo Park ,  Jae-duk Lee

IPC: H01L27/11578 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/788 ,  H01L29/66 ,  H01L27/11551 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11526

CPC classification number: H01L27/11578 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.

公开(公告)号：US09620511B2

公开(公告)日：2017-04-11

申请号：US14267909

申请日：2014-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-goo Lee ,  Young-woo Park ,  Jin-taek Park

IPC: H01L29/66 ,  H01L21/336 ,  H01L27/112 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L27/11273 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/785 ,  H01L29/7889 ,  H01L29/7926

Abstract: A vertical semiconductor device includes a channel structure extending from a substrate in a first direction perpendicular to an upper surface of the substrate, and a ground selection line, word lines, and a string selection line sequentially formed on a side surface of the channel structure in the first direction to be separated from one another. The channel structure includes a protruding region formed in a side wall portion of the channel structure between the ground selection line and the upper surface of the substrate, the protruding region protruding in a horizontal direction perpendicular to the first direction.

公开(公告)号：US09905570B2

公开(公告)日：2018-02-27

申请号：US15018477

申请日：2016-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoo-cheol Shin ,  Young-woo Park ,  Jae-duk Lee

IPC: G06K9/00 ,  H01L27/11578 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L27/1157

CPC classification number: H01L27/11578 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.

公开(公告)号：US09899412B2

公开(公告)日：2018-02-20

申请号：US15464983

申请日：2017-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-goo Lee ,  Young-woo Park ,  Jin-taek Park

IPC: H01L29/66 ,  H01L21/336 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L27/11273 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/785 ,  H01L29/7889 ,  H01L29/7926

Abstract: A vertical semiconductor device includes a channel structure extending from a substrate in a first direction perpendicular to an upper surface of the substrate, and a ground selection line, word lines, and a string selection line sequentially formed on a side surface of the channel structure in the first direction to be separated from one another. The channel structure includes a protruding region formed in a side wall portion of the channel structure between the ground selection line and the upper surface of the substrate, the protruding region protruding in a horizontal direction perpendicular to the first direction.

公开(公告)号：US20170194347A1

公开(公告)日：2017-07-06

申请号：US15464983

申请日：2017-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-goo Lee ,  Young-woo Park ,  Jin-taek Park

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L27/11273 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/785 ,  H01L29/7889 ,  H01L29/7926

Abstract: A vertical semiconductor device includes a channel structure extending from a substrate in a first direction perpendicular to an upper surface of the substrate, and a ground selection line, word lines, and a string selection line sequentially formed on a side surface of the channel structure in the first direction to be separated from one another. The channel structure includes a protruding region formed in a side wall portion of the channel structure between the ground selection line and the upper surface of the substrate, the protruding region protruding in a horizontal direction perpendicular to the first direction.