CMOS image sensor
    2.
    发明授权

    公开(公告)号:US10115759B2

    公开(公告)日:2018-10-30

    申请号:US15647664

    申请日:2017-07-12

    Abstract: A complementary metal-oxide semiconductor (CMOS) image sensor includes a device isolation layer provided in a trench of a substrate, the device isolation layer defining a pixel; and a photoelectric conversion device provided in the pixel. The device isolation layer includes a conductive layer, a tunneling layer interposed between the conductive layer and the substrate, and a trap layer interposed between the tunneling layer and the conductive layer.

    Apparatus, memory device, and method for storing multiple parameter codes for operation parameters

    公开(公告)号:US11688438B2

    公开(公告)日:2023-06-27

    申请号:US18071054

    申请日:2022-11-29

    CPC classification number: G11C7/1063 G11C7/109 G11C7/1045 G11C7/14

    Abstract: Provided are an apparatus, a memory device, and a method for storing a plurality of parameter codes for an operation parameter. The memory device includes a mode register and a control logic circuit. To set a first operating condition and a second operating condition for one operation parameter, the mode register stores a first parameter code for the operation parameter and a second parameter code, which is expressed as an offset value from the first parameter code. The control logic circuit sets the first operating condition as a current operating condition of the memory device by using the first parameter code based on a first control code and sets the second operating condition as the current operating condition of the memory device by using the first parameter code and the second parameter code based on a second control code.

    Apparatus, memory device, and method for storing multiple parameter codes for operation parameters

    公开(公告)号:US11545196B2

    公开(公告)日:2023-01-03

    申请号:US17466754

    申请日:2021-09-03

    Abstract: Provided are an apparatus, a memory device, and a method for storing a plurality of parameter codes for an operation parameter. The memory device includes a mode register and a control logic circuit. To set a first operating condition and a second operating condition for one operation parameter, the mode register stores a first parameter code for the operation parameter and a second parameter code, which is expressed as an offset value from the first parameter code. The control logic circuit sets the first operating condition as a current operating condition of the memory device by using the first parameter code based on a first control code and sets the second operating condition as the current operating condition of the memory device by using the first parameter code and the second parameter code based on a second control code.

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