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1.发明授权公开(公告)号：US11113231B2
公开(公告)日：2021-09-07
申请号：US16549968
申请日：2019-08-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngsun Song
Abstract: In a processing in memory (PIM) method using a memory device, m*n multiplicand arrangement bits are stored in m*n memory cells by copying and arranging m multiplicand bits of a multiplicand value and m*n multiplier arrangement bits are stored in m*n read-write unit circuits corresponding to the m*n memory cells by copying and arranging n multiplier bits of a multiplier value. The m*n multiplicand arrangement bits stored in the m*n memory cells are selectively read based on the m*n multiplier arrangement bits stored in the m*n read-write unit circuits, and m*n multiplication bits are stored in the m*n read-write unit circuits based on the selectively read m*n multiplicand arrangement bits. A multiplication value of the multiplicand value and the multiplier value is determined based on the m*n multiplication bits stored in the m*n read-write unit circuits.
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公开(公告)号：US20250048655A1
公开(公告)日：2025-02-06
申请号：US18737537
申请日：2024-06-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Bonjae KOO , Seulji Song , Youngsun Song
IPC: H10B99/00
Abstract: Provided is a semiconductor memory device including: cell blocks, each including a folding structure in which electrode structures and insulating structures are alternately provided, wherein the electrode structures and the insulating structures extend in a vertical direction and are connected with each other so as to have at least two U-shaped structures forming villus shapes in a plan view, the electrode structures include a vertical electrode and a switching material layer, and the cell blocks are provided in a first horizontal direction and a second horizontal direction intersecting the first horizontal direction; and a gate stack structure including gate electrodes and interlayer insulating layers that are alternately stacked in the vertical direction along sidewalls of the electrode structures.
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公开(公告)号：US09466386B2
公开(公告)日：2016-10-11
申请号：US14336343
申请日：2014-07-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyun-Wook Park , Jung-Soo Kim , Jaeyong Jeong , Kitae Park , Youngsun Song
CPC classification number: G11C16/225 , G11C16/0483 , G11C16/10
Abstract: A method of programming a storage device comprises determining whether at least one open page exists in a memory block of a nonvolatile memory device, and as a consequence of determining that at least one open page exists in the memory block, closing the at least one open page through a dummy pattern program operation, and thereafter performing a continuous writing operation on the memory block.
Abstract translation: 一种对存储设备进行编程的方法包括确定至少一个开放页面是否存在于非易失性存储器件的存储器块中，并且作为确定存储器块中存在至少一个打开页面的结果，关闭至少一个打开的 通过虚拟图案编程操作，然后对存储块进行连续写入操作。
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公开(公告)号：US20240422994A1
公开(公告)日：2024-12-19
申请号：US18653689
申请日：2024-05-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngsun Song , Seulji Song
IPC: H10B63/00
Abstract: A semiconductor memory device includes a first source line extending in a first horizontal direction, a second source line extending on the first source line in the first horizontal direction, a plurality of word line plates arranged apart from each other in a vertical direction, between the first source line and the second source line, a vertical bit line configured to penetrate the plurality of word line plates and extending in the vertical direction, a selector arranged between the plurality of word line plates and the vertical bit line, a first vertical channel transistor arranged between the vertical bit line and the first source line, and a second vertical channel transistor arranged between the vertical bit line and the second source line.
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公开(公告)号：US20250008747A1
公开(公告)日：2025-01-02
申请号：US18537013
申请日：2023-12-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Suhyun Bang , Seulji Song , Youngsun Song
Abstract: A three-dimensional memory device includes a base insulating layer on a substrate, a stack structure including word lines and first interlayer insulating layers which are alternately stacked on the base insulating layer, and a second interlayer insulating layer on an uppermost one of the word lines, bit lines that are in the stack structure and spaced apart from each other in a first direction parallel to a top surface of the substrate, each bit line including a first portion that protrudes from a top surface of the stack structure and a second portion that are in the stack structure, an outer electrode on the stack structure and on the first portions of the bit lines, and a dielectric layer between the outer electrode and the first portion of the bit line and surrounding a side surface of the first portion of the bit line in plan view.
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Patent Agency Ranking
公开(公告)号：US11443810B2
公开(公告)日：2022-09-13
申请号：US17220368
申请日：2021-04-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sooyeol Yang , Hyunggon Kim , Youngsun Song
IPC: G11C16/12 , H01L27/11582 , H01L27/11573
Abstract: A negative level shifter includes a shifting circuit and a latch circuit. The shifting circuit shifts levels of a first input signal and a second input signal to provide a first output signal and a second output signal having complementary levels at a first output node and a second output node, respectively, using low voltage transistors and high voltage transistors having different characteristics. The latch circuit, connected to the shifting circuit at the first output node and the second output node, latches the first output signal and the second output signal, receives a negative voltage having a level smaller than a ground voltage, and drives the second output signal and the first output signal complementarily to either a level of a power supply voltage or a level of the negative voltage, based on voltage levels at the first output node and the second output node, respectively.
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7.发明授权Nonvolatile memory devices and methods of programming nonvolatile memory devices 有权非易失性存储器件和非易失性存储器件编程方法公开(公告)号：US09064582B2
公开(公告)日：2015-06-23
申请号：US14316023
申请日：2014-06-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngsun Song , Bogeun Kim , Ohsuk Kwon , Kitae Park , Seung-Hwan Shin , Sangyong Yoon
CPC classification number: G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/08 , G11C16/34 , G11C16/3459
Abstract: A nonvolatile memory device includes a memory cell array, a page buffer unit which output a verify-read result, a reference current generating unit which generates a reference current signal, a page buffer decoding unit which outputs currents according to the verify-read result. The nonvolatile memory device further includes an analog bit counting unit which counts the currents, a digital adding unit which calculates an accumulated sum of the counting result, a pass/fail checking unit which outputs a pass signal or fail signal according to the calculation result, and a control unit controlling a program operation.
Abstract translation: 非易失性存储器件包括存储单元阵列，输出验证读取结果的页面缓冲器单元，产生参考电流信号的参考电流产生单元，根据验证读取结果输出电流的页面缓冲器解码单元。 非易失性存储装置还包括对电流进行计数的模拟比特计数单元，计算计数结果的累积和的数字加法单元，根据计算结果输出通过信号或失败信号的通过/失败检查单元， 以及控制程序操作的控制单元。
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公开(公告)号：US20250040145A1
公开(公告)日：2025-01-30
申请号：US18786011
申请日：2024-07-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Bonjae KOO , Seulji Song , Youngsun Song
Abstract: A semiconductor memory device is provided. The semiconductor device includes: a stacked structure with word line plates and mold insulating layers which extend in first and second horizontal directions, and are alternately stacked in a vertical direction in a cell array region and an extension region, the plurality of word line plates forming a staircase structure in the extension region; a vertical bit line extending into the stacked structure in the cell array region; a plurality of selection layers between the plurality of word line plates and the vertical bit line; and a vertical channel transistor connected to one end of the vertical bit line. A first thickness of each of the plurality of mold insulating layers is about 1.5 times to about 3 times a second thickness of each of the plurality of word line plates.
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公开(公告)号：US20240422991A1
公开(公告)日：2024-12-19
申请号：US18402552
申请日：2024-01-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngsun Song , Seulji Song
Abstract: A vertical memory device includes a memory cell structure extending primarily in a vertical direction. A resistive layer is electrically connected to a first end of the memory cell structure. A selector is electrically connected to a second end of the memory cell structure and includes a variable resistive material of which an electrical resistive value is reversibly changed in response to an electrical signal. A first bit line is located apart from the memory cell structure in the vertical direction with the resistive layer disposed therebetween and is connected to the resistive layer. A second bit line is located apart from the memory cell structure in the vertical direction with the selector disposed therebetween and is connected to the selector. A plurality of word line plates are spaced apart from each other in the vertical direction and overlapping each other in the vertical direction. Each word line plate at least partially surrounds a portion of a sidewall of the memory cell structure.
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公开(公告)号：US11321016B2
公开(公告)日：2022-05-03
申请号：US16888671
申请日：2020-05-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngsun Song
Abstract: In a method of writing data in a memory device, a plurality of duplicated bit rows is generated by performing a first duplication operation in which a plurality of bits included in write data are copied by units of bits. A plurality of duplicated bit groups is generated by performing a second duplication operation in which the plurality of duplicated bit rows is copied by units of rows. The plurality of duplicated bit groups is stored into a plurality of memory regions included in the memory device, respectively. Each of the plurality of memory regions is a region that is simultaneously sensed during a data read operation.
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