公开(公告)号：US20230420355A1

公开(公告)日：2023-12-28

申请号：US18130197

申请日：2023-04-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunkyul Oh ,  Chonghee LEE ,  Keunho JANG ,  Yunrae CHO

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/3128 ,  H01L24/13 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H10B80/00

Abstract: A semiconductor package includes a package substrate including a redistribution layer including first pads and second pads on an upper surface thereof and a solder mask layer having an opening exposing the first pads entirely and exposing at least portion of each of the second pads, a semiconductor chip on the upper surface of the package substrate and including connection pads electrically connected to the redistribution layer, connection bumps below the semiconductor chip and connecting the connection pads to the first pads, and a non-conductive film layer between the semiconductor chip and the package substrate, wherein the second pads are respectively disposed on both sides of the first pads at least in a first direction, and the connection bumps are spaced apart from the second pads and the solder mask layer in the first direction.

公开(公告)号：US20250006619A1

公开(公告)日：2025-01-02

申请号：US18756426

申请日：2024-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chonghee LEE ,  Yunrae CHO

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

Abstract: A package substrate includes a substrate base, a plurality of wiring pads, and a plurality of wiring lines. The substrate base includes a first surface and a second surface that is opposite to the first surface. The substrate base is divided into a plurality of regions. The plurality of wiring pads are arranged on the first surface of the substrate base and are apart from each other in a horizontal direction. The plurality of wiring lines are arranged on the first surface of the substrate base and extend from corresponding ones of the plurality of wiring pads, respectively. The plurality of wiring pads have different horizontal area in different regions of the substrate base.

公开(公告)号：US20230223374A1

公开(公告)日：2023-07-13

申请号：US18185702

申请日：2023-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunrae CHO ,  Jinyeol Yang ,  Jungmin Ko ,  Seungduk Baek

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/20 ,  H01L25/0655 ,  H01L24/05 ,  H01L24/29 ,  H01L24/13 ,  H01L2224/29009 ,  H01L2224/13083 ,  H01L2224/0557 ,  H01L2224/29008 ,  H01L2924/14 ,  H01L2224/0401

Abstract: An integrated circuit device includes a wiring structure, first and second inter-wiring insulating layers, redistributions patterns and a cover insulating layer. The wiring structure includes wiring layers having a multilayer wiring structure and via plugs. The first inter-wiring insulating layer that surrounds the wiring structure on a substrate. The second inter-wiring insulating layer is on the first inter-wiring insulating layer, and redistribution via plugs are connected to the wiring structure through the second inter-wiring insulating layer. The redistribution patterns includes pad patterns and dummy patterns on the second inter-wiring insulating layer. Each patterns has a thickness greater than a thickness of each wiring layer. The cover insulating layer covers some of the redistribution patterns. The dummy patterns are in the form of lines that extend in a horizontal direction parallel to the substrate.

公开(公告)号：US20250167151A1

公开(公告)日：2025-05-22

申请号：US18679992

申请日：2024-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chonghee LEE ,  Yunrae CHO

IPC: H01L23/00

Abstract: A semiconductor package includes a wiring board including a wiring pattern, a solder resist layer on a top surface of the wiring board and defining an opening that exposes the wiring pattern, solder resist patterns arranged in the opening, and a semiconductor chip electrically connected to the wiring pattern of the wiring board and mounted on the wiring board. The solder resist patterns are arranged under a first edge of one side of the semiconductor chip.

公开(公告)号：US20210066231A1

公开(公告)日：2021-03-04

申请号：US16846616

申请日：2020-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunrae CHO ,  Jinyeol YANG ,  Jungmin KO ,  Seungduk BAEK

IPC: H01L23/00

Abstract: An integrated circuit device includes a wiring structure, first and second inter-wiring insulating layers, redistributions patterns and a cover insulating layer. The wiring structure includes wiring layers having a multilayer wiring structure and via plugs. The first inter-wiring insulating layer that surrounds the wiring structure on a substrate. The second inter-wiring insulating layer is on the first inter-wiring insulating layer, and redistribution via plugs are connected to the wiring structure through the second inter-wiring insulating layer. The redistribution patterns includes pad patterns and dummy patterns on the second inter-wiring insulating layer. Each patterns has a thickness greater than a thickness of each wiring layer. The cover insulating layer covers some of the redistribution patterns. The dummy patterns are in the form of lines that extend in a horizontal direction parallel to the substrate.