公开(公告)号：US10707234B2

公开(公告)日：2020-07-07

申请号：US16204637

申请日：2018-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoon-Sung Choi ,  Dong-Il Park ,  Yuri Masuoka

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/092

Abstract: A semiconductor device comprises: a substrate; a first well region of a first conductivity type and a second well region of a second conductivity type formed horizontally adjacent to each other in the substrate; a buried insulation layer formed on the first well region and the second well region; a first semiconductor layer formed to vertically overlap the first well region, and a second semiconductor layer formed to vertically overlap the second well region, on the buried insulation layer; a first isolation layer formed between the first semiconductor layer and the second semiconductor layer on the buried insulation layer; and a conductive layer formed on the first semiconductor layer and the second semiconductor layer to extend over the first semiconductor layer and the second semiconductor layer.

公开(公告)号：US11728429B2

公开(公告)日：2023-08-15

申请号：US17549985

申请日：2021-12-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yul Lee ,  Yuri Masuoka

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L29/08

CPC classification number: H01L29/7848 ,  H01L21/28167 ,  H01L21/76264 ,  H01L29/0895 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/785 ,  H01L29/7833

Abstract: A semiconductor device includes at least one active pattern on a substrate, at least one gate electrode intersecting the at least one active pattern, source/drain regions on the at least one active pattern, the source/drain regions being on opposite sides of the at least one gate electrode, and a barrier layer between at least one of the source/drain regions and the at least one active pattern, the barrier layer being at least on bottoms of the source/drain regions and including oxygen.

公开(公告)号：US11469228B2

公开(公告)日：2022-10-11

申请号：US17146938

申请日：2021-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanwook Lee ,  Seungkwon Kim ,  Jaechul Kim ,  Younggun Ko ,  Yuri Masuoka

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/66

Abstract: Disclosed is a semiconductor device comprising a substrate including PMOSFET and NMOSFET regions, first active fins at the PMOSFET region, second active fins at the NMOSFET region, a gate electrode extending in a first direction and running across the first and second active fins, a first source/drain pattern on the first active fins and connecting the first active fins to each other, a second source/drain pattern on the second active fins and connecting the second active fins to each other, a first active contact electrically connected to the first source/drain pattern, and a second active contact electrically connected to the second source/drain pattern. A maximum width of the first active contact in the first direction is less than a maximum width of the second active in the first direction.

公开(公告)号：US10916476B2

公开(公告)日：2021-02-09

申请号：US16901484

申请日：2020-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-min Yoo ,  Sang-deok Kwon ,  Yuri Masuoka

IPC: H01L21/82 ,  H01L21/32 ,  H01L21/8234 ,  H01L29/66

Abstract: Provided are semiconductor devices having various line widths and a method of manufacturing the semiconductor device. The semiconductor device includes: a substrate including a first region and a second region, a plurality of first gate lines extending in a first direction in the first region and each having a first width in a second; a plurality of second gate lines extending in the first direction in the second region and each having a second width that is different from the first width in the second direction and a pitch that is the same as a pitch of the plurality of first gate lines; a spacer layer covering opposite side walls of each of the plurality of first gate lines and each of the plurality of second gate lines; and a first base layer arranged between the substrate and the spacer layer in the first region.

公开(公告)号：US10770355B2

公开(公告)日：2020-09-08

申请号：US16394589

申请日：2019-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-min Yoo ,  Sang-deok Kwon ,  Yuri Masuoka

IPC: H01L21/82 ,  H01L21/32 ,  H01L21/8234 ,  H01L29/66

Abstract: Provided are semiconductor devices having various line widths and a method of manufacturing the semiconductor device. The semiconductor device includes: a substrate including a first region and a second region, a plurality of first gate lines extending in a first direction in the first region and each having a first width in a second; a plurality of second gate lines extending in the first direction in the second region and each having a second width that is different from the first width in the second direction and a pitch that is the same as a pitch of the plurality of first gate lines; a spacer layer covering opposite side walls of each of the plurality of first gate lines and each of the plurality of second gate lines; and a first base layer arranged between the substrate and the spacer layer in the first region.

公开(公告)号：US20200058559A1

公开(公告)日：2020-02-20

申请号：US16394589

申请日：2019-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-min Yoo ,  Sang-deok Kwon ,  Yuri Masuoka

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/32

Abstract: Provided are semiconductor devices having various line widths and a method of manufacturing the semiconductor device. The semiconductor device includes: a substrate including a first region and a second region, a plurality of first gate lines extending in a first direction in the first region and each having a first width in a second; a plurality of second gate lines extending in the first direction in the second region and each having a second width that is different from the first width in the second direction and a pitch that is the same as a pitch of the plurality of first gate lines; a spacer layer covering opposite side walls of each of the plurality of first gate lines and each of the plurality of second gate lines; and a first base layer arranged between the substrate and the spacer layer in the first region.

公开(公告)号：US20200052116A1

公开(公告)日：2020-02-13

申请号：US16508774

申请日：2019-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNG KWON KIM ,  Yuri Masuoka

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/08 ,  H01L29/165 ,  H01L29/36 ,  H01L29/10 ,  H01L29/16

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including first through third regions, a first transistor of a first conductivity type disposed on the first region of the substrate and including a first channel layer, in which the first channel layer includes a first material, a second transistor of a second conductivity type different from the first conductivity type disposed on the second region of the substrate and including a second channel layer, in which the second channel layer includes the first material, and a third transistor of the second conductivity type disposed on the third region of the substrate and including a third channel layer, in which the third channel layer includes a second material different from the first material.

公开(公告)号：US11222978B2

公开(公告)日：2022-01-11

申请号：US16019811

申请日：2018-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yul Lee ,  Yuri Masuoka

IPC: H01L31/072 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L29/08

Abstract: A semiconductor device includes at least one active pattern on a substrate, at least one gate electrode intersecting the at least one active pattern, source/drain regions on the at least one active pattern, the source/drain regions being on opposite sides of the at least one gate electrode, and a barrier layer between at least one of the source/drain regions and the at least one active pattern, the barrier layer being at least on bottoms of the source/drain regions and including oxygen.

公开(公告)号：US09673106B2

公开(公告)日：2017-06-06

申请号：US14956522

申请日：2015-12-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： So-Yeon Kim ,  Yuri Masuoka

IPC: H01L29/423 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

CPC classification number: H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

Abstract: A semiconductor device includes a substrate including an active fin and an isolation layer thereon, a first gate structure on the active fin, the first gate structure including a first gate insulation layer pattern and a first metal pattern, and the first metal pattern having a first conductivity type and directly contacting the first gate insulation layer pattern, a first channel region at a portion of the active fin facing a bottom surface of the first gate structure, the first channel region including impurities having the first conductivity type, and first source/drain regions at upper portions of the active fin adjacent to opposite sidewalls of the first gate structure, the first source/drain regions including impurities having a second conductivity type different from the first conductivity type.