公开(公告)号：US06640283B2

公开(公告)日：2003-10-28

申请号：US10050736

申请日：2002-01-16

申请人： Samuel Naffziger ,  Wayne Kever

发明人： Samuel Naffziger ,  Wayne Kever

IPC分类号： G06F1300

CPC分类号： G06F12/0802 ,  G06F2212/401

摘要： A compression engine for a cache memory subsystem has a pointer into cache tag memory and cache data memory and an interface coupled to the pointer and capable of being coupled to cache tag memory, and cache data memory. The interface reads tag information and uncompressed data from the cache and writes modified tag information and compressed data to the cache. The compression engine also has compression logic for generating compressed data and generate compression successful information, and tag line update circuitry for generating modified tag information according to the compression successful information and the tag information. Also disclosed is a cache subsystem for a computer system embodying the compression engine, and a method of compressing cache using the compression engine.

公开(公告)号：US06933611B2

公开(公告)日：2005-08-23

申请号：US10629055

申请日：2003-07-29

申请人： Wayne Kever

发明人： Wayne Kever

IPC分类号： H01L21/48 ,  H01L21/66 ,  H01L23/48 ,  H01L21/44 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L22/20 ,  H01L21/485 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/014 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

摘要： Selective application of solder bumps in an integrated circuit package. Solder bumps are selectively applied in a solder bump integrated circuit packaging process so that portions of a circuit can be effectively disabled. The bumps may be selectively applied either to a die or to the substrate using multiple solder masks, one for each pattern of solder bumps desired or can be otherwise applied in multiple patterns depending upon which portions of the circuitry are to be active and which are to be disabled.

摘要翻译： 在集成电路封装中选择性地应用焊料凸块。 焊料凸块选择性地应用于焊料凸块集成电路封装工艺中，使得可以有效地阻止电路的部分。 可以使用多个焊料掩模将凸块选择性地施加到管芯或衬底上，对于每个所需的焊料凸块图案，可以使用一个焊料掩模，或者可以以多个图案施加凸块，这取决于电路的哪些部分将是活动的， 被禁用

公开(公告)号：US20050081167A1

公开(公告)日：2005-04-14

申请号：US10681815

申请日：2003-10-08

申请人： Wayne Kever ,  Kenneth Koch

发明人： Wayne Kever ,  Kenneth Koch

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： Processes, software and systems asymmetrically shrink a layout for a VLSI circuit design. A first VLSI circuit design layout, defined by a first fabrication process with first design rules, is asymmetrically scaled to a second VLSI circuit design layout defined by a second fabrication process with second design rules. Layouts of one or more leaf cells of the second VLSI circuit design layout are processed to ensure conformity to the second design rules.

摘要翻译： 过程，软件和系统不对称地缩小了VLSI电路设计的布局。 由具有第一设计规则的第一制造过程定义的第一VLSI电路设计布局被不对称地缩放到由具有第二设计规则的第二制造工艺定义的第二VLSI电路设计布局。 处理第二VLSI电路设计布局的一个或多个叶单元的布局以确保符合第二设计规则。

公开(公告)号：US06735673B2

公开(公告)日：2004-05-11

申请号：US10043789

申请日：2002-01-10

申请人： Wayne Kever

发明人： Wayne Kever

IPC分类号： G06F1200

CPC分类号： G06F12/0802 ,  G06F12/0886 ,  G06F2212/401

摘要： A method for storing lines of data in a data array of a cache memory mapped to a main memory of a processing system. The data array includes data storage lines having equal lengths. The method includes compressing at least one of the lines of data, fitting the compressed line of data within a subsection of one of the data storage lines, and pointing to the subsection using a tag array. When lines of data are stored in compressed form, more lines can fit into the cache, and a probability of a cache hit is increased.

摘要翻译： 一种在映射到处理系统的主存储器的高速缓冲存储器的数据阵列中存储数据行的方法。 数据阵列包括具有相等长度的数据存储线。 该方法包括压缩数据行中的至少一行，将压缩的数据线拟合在数据存储线之一的子部分内，并使用标签数组指向子部分。 当数据行以压缩形式存储时，更多的行可以适应高速缓存，并且高速缓存命中的概率增加。

公开(公告)号：US09163594B1

公开(公告)日：2015-10-20

申请号：US14285699

申请日：2014-05-23

申请人： Wayne Kever

发明人： Wayne Kever

IPC分类号： F02M35/10 ,  F02M35/104 ,  F02B27/02 ,  F02B75/22

CPC分类号： F02M35/10091 ,  F02B27/006 ,  F02B27/02 ,  F02B75/22 ,  F02M35/10072 ,  F02M35/10196 ,  F02M35/104 ,  F02M35/116 ,  F02M35/161 ,  Y02T10/146

摘要： A manifold including first and second divider bodies each having a carburetor mounting flange. The first divider body includes a first and a second plenum, and the second divider body includes a third and a fourth plenum. A first pair of runners extends from the first port flange to the first plenum; a second pair of runners extends from the first port flange to the third plenum; a third pair of runners extends from the second port flange to the second plenum; and a fourth pair of runners extends from the second port flange to the fourth plenum. Accordingly, in operation, each plenum will present only one carburetor venturi to the cylinder in a low-RPM, low-throttle opening induction event, thus keeping the peak velocity through the carburetor's venturi high even at low RPM.

摘要翻译： 一种歧管，包括第一和第二分隔体，每个分隔体具有化油器安装凸缘。 第一分隔体包括第一和第二增压室，第二分隔体包括第三和第四增压室。 第一对流道从第一端口法兰延伸到第一集气室; 第二对流道从第一端口凸缘延伸到第三集气室; 第三对流道从第二端口凸缘延伸到第二增压室; 并且第四对流道从第二端口凸缘延伸到第四集气室。 因此，在运行中，每个气室将仅以一个低转速，低节气门开启感应事件的方式，在汽缸中仅显示一个化油器文丘里管，因此即使在低转速下也能保持通过化油器文丘里管的高峰速度。

公开(公告)号：US08733312B1

公开(公告)日：2014-05-27

申请号：US13302451

申请日：2011-11-22

申请人： Wayne Kever

发明人： Wayne Kever

IPC分类号： F02M35/10

CPC分类号： F02M35/10091 ,  F02B27/006 ,  F02B27/02 ,  F02B75/22 ,  F02M35/10072 ,  F02M35/10196 ,  F02M35/104 ,  F02M35/116 ,  F02M35/161 ,  Y02T10/146

摘要： A manifold including first and second divider bodies each having a carburetor mounting flange. The first divider body includes a first and a second plenum, and the second divider body includes a third and a fourth plenum. A first pair of runners extends from the first port flange to the first plenum; a second pair of runners extends from the first port flange to the third plenum; a third pair of runners extends from the second port flange to the second plenum; and a fourth pair of runners extends from the second port flange to the fourth plenum. Accordingly, in operation, each plenum will present only one carburetor venturi to the cylinder in a low-RPM, low-throttle opening induction event, thus keeping the peak velocity through the carburetor's venturi high even at low RPM.

摘要翻译： 一种歧管，包括第一和第二分隔体，每个分隔体具有化油器安装凸缘。 第一分隔体包括第一和第二增压室，第二分隔体包括第三和第四增压室。 第一对流道从第一端口法兰延伸到第一集气室; 第二对流道从第一端口凸缘延伸到第三集气室; 第三对流道从第二端口凸缘延伸到第二增压室; 并且第四对流道从第二端口凸缘延伸到第四集气室。 因此，在运行中，每个气室将仅以一个低转速，低节气门开启感应事件的方式，在汽缸中仅显示一个化油器文丘里管，因此即使在低转速下也能保持通过化油器文丘里管的高峰速度。

公开(公告)号：US06895497B2

公开(公告)日：2005-05-17

申请号：US10092714

申请日：2002-03-06

申请人： Eric S. Fetzer ,  Wayne Kever ,  Eric DeLano

发明人： Eric S. Fetzer ,  Wayne Kever ,  Eric DeLano

IPC分类号： G06F9/38

CPC分类号： G06F9/3851

摘要： A multiple dispatch processor has several instruction fetch units, each for providing a stream of instructions to an instruction decode and dispatch unit. The processor also has an resource allocation unit, and multiple resources such as combined integer and address execution pipelines and floating point execution pipelines. Each instruction decode and dispatch unit requests resources needed to perform an instruction of the resource allocation unit, which arbitrates among the multiple instruction decode and dispatch units.

摘要翻译： 多调度处理器具有多个指令获取单元，每个指令提取单元用于向指令解码和调度单元提供指令流。 处理器还具有资源分配单元，以及多个资源，例如组合的整数和地址执行管线和浮点执行管线。 每个指令解码和调度单元请求执行资源分配单元的指令所需的资源，该指令在多个指令解码和调度单元之间进行仲裁。

公开(公告)号：US06645841B2

公开(公告)日：2003-11-11

申请号：US10016039

申请日：2001-11-16

申请人： Wayne Kever

发明人： Wayne Kever

IPC分类号： H01L2144

CPC分类号： H01L22/20 ,  H01L21/485 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/014 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

摘要： Selective application of solder bumps in an integrated circuit package. Solder bumps are selectively applied in a solder bump integrated circuit packaging process so that portions of a circuit can be effectively disabled. The bumps may be selectively applied either to a die or to the substrate using multiple solder masks, one for each pattern of solder bumps desired or can be otherwise applied in multiple patterns depending upon which portions of the circuitry are to be active and which are to be disabled.

摘要翻译： 在集成电路封装中选择性地应用焊料凸块。 焊料凸块选择性地应用于焊料凸块集成电路封装工艺中，使得可以有效地阻止电路的部分。 可以使用多个焊料掩模将凸块选择性地施加到管芯或衬底上，对于每个所需的焊料凸块图案，可以使用一个焊料掩模，或者可以以多个图案施加凸块，这取决于电路的哪些部分将是活动的， 被禁用