公开(公告)号：US09721653B2

公开(公告)日：2017-08-01

申请号：US15254792

申请日：2016-09-01

Applicant: SanDisk Technologies LLC

Inventor： Tianhong Yan ,  George Samachisa

IPC: G11C11/00 ,  G11C13/00 ,  B82Y10/00 ,  G11C11/56 ,  G11C13/02 ,  H01L27/24 ,  H01L45/00 ,  G11C16/10 ,  G11C11/06 ,  H01L23/528

CPC classification number: G11C13/0007 ,  B82Y10/00 ,  G11C11/06035 ,  G11C11/5614 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/025 ,  G11C16/10 ,  G11C2013/0045 ,  G11C2013/0088 ,  G11C2213/19 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/55 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/78 ,  H01L23/528 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/06 ,  H01L45/065 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/146 ,  H01L45/148 ,  H01L45/149

Abstract: A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

公开(公告)号：US20170004881A1

公开(公告)日：2017-01-05

申请号：US15254792

申请日：2016-09-01

Applicant: SanDisk Technologies LLC

Inventor： Tianhong Yan ,  George Samachisa

IPC: G11C13/00 ,  H01L23/528 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/0007 ,  B82Y10/00 ,  G11C11/06035 ,  G11C11/5614 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/025 ,  G11C16/10 ,  G11C2013/0045 ,  G11C2013/0088 ,  G11C2213/19 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/55 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/78 ,  H01L23/528 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/06 ,  H01L45/065 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/146 ,  H01L45/148 ,  H01L45/149

Abstract: A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Abstract translation: 特别适用于响应于在其上施加电压差而可逆地改变电导水平的存储元件的三维阵列。 存储元件跨越位于半导体衬底上方不同距离的多个平面形成。 所有平面的存储元件所连接的位线从衬底垂直定向并穿过多个平面。

公开(公告)号：US09672916B2

公开(公告)日：2017-06-06

申请号：US15083224

申请日：2016-03-28

Applicant: SANDISK TECHNOLOGIES, LLC

Inventor： Yanli Zhang ,  George Samachisa ,  Johann Alsmeier ,  Jian Chen

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G11C11/56

CPC classification number: G11C16/0483 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/26

Abstract: Methods for performing memory operations on a memory array that includes inverted NAND strings are described. The memory operations may include erase operations, read operations, programming operations, program verify operations, and erase verify operations. An inverted NAND string may include a string of inverted floating gate transistors or a string of inverted charge trap transistors. In one embodiment, an inverted floating gate transistor may include a tunneling layer between a floating gate of the inverted floating gate transistor and a control gate of the inverted floating gate transistor. The arrangement of the tunneling layer between the floating gate and the control gate allows electrons to be added to or removed from the floating gate via F-N tunneling between the floating gate and the control gate. The inverted NAND string may be formed above a substrate and oriented such that the inverted NAND string is orthogonal to the substrate.