公开(公告)号：US10037810B1

公开(公告)日：2018-07-31

申请号：US15634006

申请日：2017-06-27

Applicant: SanDisk Technologies LLC

Inventor： Hemant Shukla ,  Saurabh Kumar Singh ,  Sridhar Yadala ,  Raul-Adrian Cernea ,  Anirudh Amarnath

IPC: G11C16/04 ,  G11C16/30 ,  G11C16/10 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/30 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32

Abstract: The peak voltage at which a voltage-setting transistor is driven is reduced while the body effect of the transistor is also compensated. The voltage-setting transistor is driven at an initial level and then coupled higher by a capacitor which is connected to the control gate of the voltage-setting transistor. The amount of coupling can vary as a function of an assigned data state of a memory cell connected to the transistor by a source line and/or bit line. The capacitor may have a body which is common to a set of memory cells. The voltage can be set prior to applying a program voltage to the control gate of a memory cell to control a programming speed of the memory cell based on its assigned data state. The voltage can also be set in connection with a sensing operation.