公开(公告)号：US10290804B2

公开(公告)日：2019-05-14

申请号：US15637357

申请日：2017-06-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ricardo Ruiz ,  Jeffrey Lille ,  Mac D. Apodaca ,  Derek Stewart ,  Lei Wan ,  Bruce Terris

IPC: H01L21/00 ,  H01L45/00 ,  H01L27/24 ,  H01L21/02

Abstract: Resistive memory cells containing nanoparticles are formed between two electrodes. The nanoparticles may be embedded in a matrix or sintered together without a matrix. The memory cells may be projected memory cells or barrier modulated cells. Polymeric ligands may be used to deposit the nanoparticles over a substrate, followed by an optional removal or replacement of the polymeric ligands.

公开(公告)号：US10217505B1

公开(公告)日：2019-02-26

申请号：US15692780

申请日：2017-08-31

Applicant: SanDisk Technologies LLC

Inventor： Mac D. Apodaca ,  Luiz Franca-Neto ,  Jordan Katine

IPC: G11C11/16 ,  G11C11/4096 ,  G11C11/56 ,  G11C13/00 ,  H03K19/16 ,  H01L45/00

Abstract: Apparatuses, systems, and methods are disclosed for a chip with phase change memory (PCM) and magnetoresistive random access memory (MRAM). An apparatus includes a semiconductor circuit formed over a substrate of a chip. An apparatus includes a PCM array formed over a semiconductor circuit. An apparatus includes an MRAM array formed over a semiconductor circuit.

公开(公告)号：US11081174B2

公开(公告)日：2021-08-03

申请号：US16912719

申请日：2020-06-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhaoqiang Bai ,  Mac D. Apodaca ,  Michael K. Grobis ,  Michael Nicolas Albert Tran ,  Neil Leslie Robertson ,  Gerardo A. Bertero

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: A two-step SET pulse may be applied to a phase change material of a phase change memory cell in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.

公开(公告)号：US10249682B2

公开(公告)日：2019-04-02

申请号：US15684141

申请日：2017-08-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Luiz M. Franca-Neto ,  Mac D. Apodaca ,  Christopher J. Petti

IPC: G11C11/22 ,  H01L27/24 ,  G03G5/024 ,  H01L29/786 ,  H01L27/108 ,  H01L29/66 ,  G11C13/00

Abstract: A non-volatile storage apparatus is proposed that includes a plurality of serially connected non-volatile reversible resistance-switching memory cells, a plurality of word lines such that each of the memory cells is connected to a different word line, a bit line connected to a first end of the serially connected memory cells and a switch connected to a second end of the serially connected memory cells. In one embodiment, the memory cells include a reversible resistance-switching structure comprising a first material, a second material and a reversible resistance-switching interface between the first material and the second material, a channel, and means for switching current between current flowing through the channel and current flowing through the reversible resistance-switching interface in order to program and read the reversible resistance-switching interface. A process for manufacturing the memory is also disclosed.

公开(公告)号：US20190067370A1

公开(公告)日：2019-02-28

申请号：US15684162

申请日：2017-08-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Luiz M. Franca-Neto ,  Mac D. Apodaca ,  Christopher J. Petti

IPC: H01L27/24 ,  H01L27/32

Abstract: A non-volatile storage apparatus is proposed that includes a plurality of serially connected non-volatile reversible resistance-switching memory cells, a plurality of word lines such that each of the memory cells is connected to a different word line, a bit line connected to a first end of the serially connected memory cells and a switch connected to a second end of the serially connected memory cells. In one embodiment, the memory cells include a reversible resistance-switching structure comprising a first material, a second material and a reversible resistance-switching interface between the first material and the second material, a channel, and means for switching current between current flowing through the channel and current flowing through the reversible resistance-switching interface in order to program and read the reversible resistance-switching interface. A process for manufacturing the memory is also disclosed.

公开(公告)号：US10283562B2

公开(公告)日：2019-05-07

申请号：US15684162

申请日：2017-08-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Luiz M. Franca-Neto ,  Mac D. Apodaca ,  Christopher J. Petti

IPC: G11C11/00 ,  H01L27/24 ,  H01L27/32 ,  H01L27/112 ,  G11C13/00

Abstract: A non-volatile storage apparatus is proposed that includes a plurality of serially connected non-volatile reversible resistance-switching memory cells, a plurality of word lines such that each of the memory cells is connected to a different word line, a bit line connected to a first end of the serially connected memory cells and a switch connected to a second end of the serially connected memory cells. In one embodiment, the memory cells include a reversible resistance-switching structure comprising a first material, a second material and a reversible resistance-switching interface between the first material and the second material, a channel, and means for switching current between current flowing through the channel and current flowing through the reversible resistance-switching interface in order to program and read the reversible resistance-switching interface. A process for manufacturing the memory is also disclosed.

公开(公告)号：US20190067369A1

公开(公告)日：2019-02-28

申请号：US15684150

申请日：2017-08-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Luiz M. Franca-Neto ,  Mac D. Apodaca ,  Christopher J. Petti

IPC: H01L27/24 ,  H01L27/112

Abstract: A non-volatile storage apparatus is proposed that includes a plurality of serially connected non-volatile reversible resistance-switching memory cells, a plurality of word lines such that each of the memory cells is connected to a different word line, a bit line connected to a first end of the serially connected memory cells and a switch connected to a second end of the serially connected memory cells. In one embodiment, the memory cells include a reversible resistance-switching structure comprising a first material, a second material and a reversible resistance-switching interface between the first material and the second material, a channel, and means for switching current between current flowing through the channel and current flowing through the reversible resistance-switching interface in order to program and read the reversible resistance-switching interface. A process for manufacturing the memory is also disclosed.

公开(公告)号：US10217795B1

公开(公告)日：2019-02-26

申请号：US15684150

申请日：2017-08-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Luiz M. Franca-Neto ,  Mac D. Apodaca ,  Christopher J. Petti

IPC: G11C11/00 ,  H01L27/24 ,  H01L27/112 ,  H01L27/32 ,  G11C13/00

Abstract: A non-volatile storage apparatus is proposed that includes a plurality of serially connected non-volatile reversible resistance-switching memory cells, a plurality of word lines such that each of the memory cells is connected to a different word line, a bit line connected to a first end of the serially connected memory cells and a switch connected to a second end of the serially connected memory cells. In one embodiment, the memory cells include a reversible resistance-switching structure comprising a first material, a second material and a reversible resistance-switching interface between the first material and the second material, a channel, and means for switching current between current flowing through the channel and current flowing through the reversible resistance-switching interface in order to program and read the reversible resistance-switching interface. A process for manufacturing the memory is also disclosed.

公开(公告)号：US10147876B1

公开(公告)日：2018-12-04

申请号：US15693376

申请日：2017-08-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lidu Huang ,  Mac D. Apodaca ,  Toshiki Hirano ,  Ailian Zhao ,  Guy Charles Wicker ,  Federico Nardi

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

Abstract: Systems and methods for providing a phase change memory that includes a phase change material, such as a chalcogenide material, in series with a heating element that comprises multiple thermal interfaces are described. The multiple thermal interfaces may cause the heating element to have a reduced bulk thermal conductivity or a lower heat transfer rate across the heating element without a corresponding reduction in electrical conductivity. The phase change material may comprise a germanium-antimony-tellurium compound or a chalcogenide glass. The heating element may include a plurality of conducting layers with different thermal conductivities. In some cases, the heating element may include two or more conducting layers in which the conducting layers comprise the same electrically conductive material or compound but are deposited or formed using different temperatures, carrier gas pressures, flow rates, and/or film thicknesses to create thermal interfaces between the two or more conducting layers.

公开(公告)号：US20200342926A1

公开(公告)日：2020-10-29

申请号：US16396710

申请日：2019-04-28

Applicant: SanDisk Technologies LLC

Inventor： Jordan A. Katine ,  Mac D. Apodaca ,  Christopher J. Petti

IPC: G11C11/16 ,  H01L43/12 ,  H01L27/22 ,  H01L43/10 ,  H01L43/08 ,  H01L43/02

Abstract: A memory array is provided that includes a first memory level including a plane of first selector material, and a plurality of first memory cells each including a corresponding first magnetic memory element coupled in series with a corresponding first selector element. Each first selector element includes a region of the plane of first selector material.