利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

47 条记录 (耗时 0.02 秒)

    Dynamic random access memory of semiconductor device and method for manufacturing the same
    1.
    发明申请
    Dynamic random access memory of semiconductor device and method for manufacturing the same 失效
    半导体器件的动态随机存取存储器及其制造方法

    公开(公告)号：US20060024888A1

    公开(公告)日：2006-02-02

    申请号：US11165180

    申请日：2005-06-24

    申请人： Sang Lee ,  Yil Kim ,  Jin Ahn

    发明人： Sang Lee ,  Yil Kim ,  Jin Ahn

    IPC分类号： H01L21/336

    CPC分类号： H01L29/513 ,  H01L21/823462 ,  H01L27/10873 ,  H01L29/517

    摘要： The present invention discloses an improved DRAM of semiconductor device and method for manufacturing the same wherein an ONO (oxide-nitride-oxide) structure for trapping electrons or holes used in a non-volatile memory is employed in a gate insulating film of the DRAM to reduce impurity concentrations of a channel region and a well region.

    摘要翻译： 本发明公开了一种改进的半导体器件的DRAM及其制造方法，其中在DRAM的栅极绝缘膜中采用用于捕获在非易失性存储器中使用的电子或空穴的ONO（氧化物 - 氮化物 - 氧化物）结构 降低通道区域和阱区域的杂质浓度。

    Dynamic random access memory of semiconductor device and method for manufacturing the same
    2.
    发明申请
    Dynamic random access memory of semiconductor device and method for manufacturing the same 审中-公开
    半导体器件的动态随机存取存储器及其制造方法

    公开(公告)号：US20070066016A1

    公开(公告)日：2007-03-22

    申请号：US11603054

    申请日：2006-11-22

    申请人： Sang Lee ,  Yil Kim ,  Jin Ahn

    发明人： Sang Lee ,  Yil Kim ,  Jin Ahn

    IPC分类号： H01L21/336

    CPC分类号： H01L29/513 ,  H01L21/823462 ,  H01L27/10873 ,  H01L29/517

    摘要： The present invention discloses an improved DRAM of semiconductor device and method for manufacturing the same wherein an ONO (oxide-nitride-oxide) structure for trapping electrons or holes used in a non-volatile memory is employed in a gate insulating film of the DRAM to reduce impurity concentrations of a channel region and a well region.

    摘要翻译： 本发明公开了一种改进的半导体器件的DRAM及其制造方法，其中在DRAM的栅极绝缘膜中采用用于捕获在非易失性存储器中使用的电子或空穴的ONO（氧化物 - 氮化物 - 氧化物）结构 降低通道区域和阱区域的杂质浓度。

    Transistor and method for manufacturing the same
    3.
    发明申请
    Transistor and method for manufacturing the same 有权
    晶体管及其制造方法

    公开(公告)号：US20050202643A1

    公开(公告)日：2005-09-15

    申请号：US10876477

    申请日：2004-06-28

    申请人： Sang Lee ,  Yil Kim ,  Jin Ahn ,  Young Park

    发明人： Sang Lee ,  Yil Kim ,  Jin Ahn ,  Young Park

    IPC分类号： H01L21/8247 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L21/28282 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/7923

    摘要： A transistor and a method for manufacturing the same are disclosed. One cell transistor having SIS (silicon-insulator-silicon) structure and two cell transistors having SONOS (silicon-oxide-nitride-oxide-silicon) structure constitute the transistor of the present invention which can store 2 bits. The cell transistor having SIS structure and the cell transistors having SONOS (silicon-oxide-nitride-oxide-silicon) structure share one common gate electrode so that the transistor of the present invention requires only one voltage generation and control circuit.

    摘要翻译： 公开了晶体管及其制造方法。 具有SIS（硅 - 绝缘体 - 硅）结构的一个单元晶体管和具有SONOS（氧化硅 - 氧化物 - 氧化物 - 硅）结构的两个单元晶体管构成了可以存储2位的本发明的晶体管。 具有SIS结构的单元晶体管和具有SONOS（氧化硅 - 氮化物 - 氧化物 - 硅））结构的单元晶体管共享一个公共栅电极，使得本发明的晶体管仅需要一个电压产生和控制电路。

    RFID device having nonvolatile ferroelectric memory device
    6.
    发明申请
    RFID device having nonvolatile ferroelectric memory device 有权
    具有非易失性铁电存储装置的RFID装置

    公开(公告)号：US20070018821A1

    公开(公告)日：2007-01-25

    申请号：US11325486

    申请日：2006-01-05

    申请人： Hee Kang ,  Jin Ahn

    发明人： Hee Kang ,  Jin Ahn

    IPC分类号： G08B13/14

    CPC分类号： G06K19/0723 ,  G06K19/0701

    摘要： A RFID device has a nonvolatile ferroelectric memory including a memory cell array area supplied only with a high voltage and a peripheral area supplied with a low voltage, thereby reducing power consumption. The RFID device includes an antenna adapted and configured to transceive a radio frequency signal from an external communication apparatus, an analog block adapted and configured to generate a power voltage in response to the radio frequency signal received from the antenna, a digital block adapted and configured to receive the power voltage from the analog block, transmit a response signal to the analog block and output a memory control signal, and a memory adapted and configured to generate a high voltage with the power voltage and access data in response to the memory control signal.

    摘要翻译： RFID装置具有非易失性铁电存储器，其包括仅供给高电压的存储单元阵列区域和供给低电压的周边区域，从而降低功耗。 RFID设备包括适于并配置为收发来自外部通信设备的射频信号的天线，适于并配置为响应于从天线接收的射频信号而产生电力电压的模拟块，适配和配置的数字块 从模拟块接收电源电压，将响应信号发送到模拟块并输出存储器控制信号，以及存储器，其被配置为响应于存储器控制信号而产生具有电源电压和访问数据的高电压 。

    Built-in type upper/lower electrode multi-layer part and method of manufacturing thereof
    7.
    发明申请
    Built-in type upper/lower electrode multi-layer part and method of manufacturing thereof 审中-公开
    内置型上下电极多层部件及其制造方法

    公开(公告)号：US20060291138A1

    公开(公告)日：2006-12-28

    申请号：US11472335

    申请日：2006-06-22

    申请人： Sung Kang ,  Jin Ahn ,  Suk Cho ,  Young Choi ,  Hae Chung ,  Chang Shim

    发明人： Sung Kang ,  Jin Ahn ,  Suk Cho ,  Young Choi ,  Hae Chung ,  Chang Shim

    IPC分类号： H01G4/236

    CPC分类号： H01G4/30 ,  H01G4/012 ,  H01G4/232

    摘要： The present invention relates to a method of manufacturing a built-in type upper/lower electrode multi-layer part including alternately laminating a first ceramic sheet having a first internal electrode pattern formed thereon and a second ceramic sheet having a second internal electrode pattern formed thereon so as to form a first multi-layer sheet product; forming first and second via holes on the first multi-layer sheet product, the first and second via holes respectively connecting the first and second internal electrode patterns; respectively joining third and fourth ceramic sheets having no internal electrode pattern on the upper and lower portions of the first multi-layer sheet product so as to form a second multi-layer sheet product, the third and fourth ceramic sheets having third and fourth via holes formed to correspond to the first and second via holes; and filling a conductive paste in the first to fourth via holes.

    摘要翻译： 本发明涉及一种制造内置型上下电极多层部件的方法，该方法包括交替层叠形成有第一内部电极图案的第一陶瓷片和形成有第二内部电极图案的第二陶瓷片 以形成第一多层片材制品; 在第一多层片材产品上形成第一和第二通孔，分别连接第一和第二内部电极图案的第一和第二通孔; 分别在第一多层片材的上部和下部接合不具有内部电极图案的第三和第四陶瓷片，以形成第二多层片材产品，第三和第四陶瓷片具有第三和第四通孔 形成为对应于第一和第二通孔; 并在第一至第四通孔中填充导电膏。

    RFID device having nonvolatile ferroelectric memory device
    8.
    发明申请
    RFID device having nonvolatile ferroelectric memory device 有权

    公开(公告)号：US20060268631A1

    公开(公告)日：2006-11-30

    申请号：US11320986

    申请日：2005-12-30

    申请人： Hee Kang ,  Jin Ahn

    发明人： Hee Kang ,  Jin Ahn

    IPC分类号： G11C7/00

    CPC分类号： G11C11/22 ,  G11C7/16 ,  G11C8/10

    摘要： A RFID device having a nonvolatile ferroelectric memory regulates bit line capacitance to optimize a bit line sensing margin and minimize power consumption. The RFID device having an analog block adapted and configured to transmit and receive a radio frequency signal to/from an external communication apparatus, a digital block adapted and configured to receive a power voltage and the radio frequency signal from the analog block, transmit a response signal to the analog block and output a memory control signal, and a memory adapted and configured to store data and regulate bit line capacitance.

    Nonvolatile semiconductor memory device
    9.
    发明申请
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US20060268622A1

    公开(公告)日：2006-11-30

    申请号：US11296431

    申请日：2005-12-08

    申请人： Hee Kang ,  Jin Ahn

    发明人： Hee Kang ,  Jin Ahn

    IPC分类号： G11C11/34

    CPC分类号： G11C11/413 ,  G11C7/20 ,  G11C14/00 ,  G11C14/0063 ,  H01L29/7881

    摘要： A nonvolatile semiconductor memory device is provided for a high-powered system without the need for an additional system setting process to set the system initialization state after power-on to the previous state. The nonvolatile semiconductor memory device comprises a pull-up driving unit configured to include a plurality of nonvolatile cells for storing inputted data and to pull up a storage node, a pull-down driving unit configured to pull down the storage node, and a plurality of data registers including a data input/output unit configured to selectively input/output data between a bit line and the storage node depending on a voltage applied to a word line.

    摘要翻译： 为大功率系统提供非易失性半导体存储器件，而不需要额外的系统设置过程，以在上电之后将系统初始化状态设置为先前状态。 非易失性半导体存储器件包括：上拉驱动单元，被配置为包括用于存储输入数据和上拉存储节点的多个非易失性单元，被配置为将存储节点拉下来的下拉驱动单元，以及多个 数据寄存器，包括数据输入/输出单元，其配置为根据施加到字线的电压来选择性地在位线和存储节点之间输入/输出数据。